simops.c

这个是LINUX下的GDB调度工具的源码

  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* srli */
void
OP_3001 ()
{
  int64 tmp;
  if (OP[1] == 0)
    OP[1] = 16;

  trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
  tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
  SET_ACC (OP[0], tmp);
  trace_output_40 (tmp);
}

/* srx */
void
OP_4609 ()
{
  uint16 tmp;
  trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
  tmp = PSW_F0 << 15;
  tmp = ((GPR (OP[0]) >> 1) | tmp);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* st */
void
OP_34000000 ()
{
  uint16 addr = OP[1] + GPR (OP[2]);
  trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr, GPR (OP[0]));
  trace_output_void ();
}

/* st */
void
OP_6800 ()
{
  uint16 addr = GPR (OP[1]);
  trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr, GPR (OP[0]));
  trace_output_void ();
}

/* st */
/* st Rsrc1,@-SP */
void
OP_6C1F ()
{
  uint16 addr = GPR (OP[1]) - 2;
  trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
  if (OP[1] != 15)
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
      State.exception = SIGILL;
      return;
    }
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr, GPR (OP[0]));
  SET_GPR (OP[1], addr);
  trace_output_void ();
}

/* st */
void
OP_6801 ()
{
  uint16 addr = GPR (OP[1]);
  trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr, GPR (OP[0]));
  INC_ADDR (OP[1], 2);
  trace_output_void ();
}

/* st */
void
OP_6C01 ()
{
  uint16 addr = GPR (OP[1]);
  trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
  if ( OP[1] == 15 )
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
      State.exception = SIGILL;
      return;
    }
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr, GPR (OP[0]));
  INC_ADDR (OP[1], -2);
  trace_output_void ();
}

/* st */
void
OP_36010000 ()
{
  uint16 addr = OP[1];
  trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr, GPR (OP[0]));
  trace_output_void ();
}

/* st2w */
void
OP_35000000 ()
{
  uint16 addr = GPR (OP[2])+ OP[1];
  trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr + 0, GPR (OP[0] + 0));
  SW (addr + 2, GPR (OP[0] + 1));
  trace_output_void ();
}

/* st2w */
void
OP_6A00 ()
{
  uint16 addr = GPR (OP[1]);
  trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr + 0, GPR (OP[0] + 0));
  SW (addr + 2, GPR (OP[0] + 1));
  trace_output_void ();
}

/* st2w */
void
OP_6E1F ()
{
  uint16 addr = GPR (OP[1]) - 4;
  trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
  if ( OP[1] != 15 )
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
      State.exception = SIGILL;
      return;
    }
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr + 0, GPR (OP[0] + 0));
  SW (addr + 2, GPR (OP[0] + 1));
  SET_GPR (OP[1], addr);
  trace_output_void ();
}

/* st2w */
void
OP_6A01 ()
{
  uint16 addr = GPR (OP[1]);
  trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr + 0, GPR (OP[0] + 0));
  SW (addr + 2, GPR (OP[0] + 1));
  INC_ADDR (OP[1], 4);
  trace_output_void ();
}

/* st2w */
void
OP_6E01 ()
{
  uint16 addr = GPR (OP[1]);
  trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
  if ( OP[1] == 15 )
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
      State.exception = SIGILL;
      return;
    }
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr + 0, GPR (OP[0] + 0));
  SW (addr + 2, GPR (OP[0] + 1));
  INC_ADDR (OP[1], -4);
  trace_output_void ();
}

/* st2w */
void
OP_37010000 ()
{
  uint16 addr = OP[1];
  trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  SW (addr + 0, GPR (OP[0] + 0));
  SW (addr + 2, GPR (OP[0] + 1));
  trace_output_void ();
}

/* stb */
void
OP_3C000000 ()
{
  trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
  SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
  trace_output_void ();
}

/* stb */
void
OP_7800 ()
{
  trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
  SB (GPR (OP[1]), GPR (OP[0]));
  trace_output_void ();
}

/* stop */
void
OP_5FE0 ()
{
  trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
  State.exception = SIG_D10V_STOP;
  trace_output_void ();
}

/* sub */
void
OP_0 ()
{
  uint16 a = GPR (OP[0]);
  uint16 b = GPR (OP[1]);
  uint16 tmp = (a - b);
  trace_input ("sub", OP_REG, OP_REG, OP_VOID);
  /* see ../common/sim-alu.h for a more extensive discussion on how to
     compute the carry/overflow bits. */
  SET_PSW_C (a >= b);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* sub */
void
OP_1001 ()
{
  int64 tmp;

  trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
  tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
  if (PSW_ST)
    {
      if (tmp > SEXT40(MAX32))
	tmp = (MAX32);
      else if (tmp < SEXT40(MIN32))
	tmp = (MIN32);
      else
	tmp = (tmp & MASK40);
    }
  else
    tmp = (tmp & MASK40);
  SET_ACC (OP[0], tmp);

  trace_output_40 (tmp);
}

/* sub */

void
OP_1003 ()
{
  int64 tmp;

  trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
  tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
  if (PSW_ST)
    {
      if (tmp > SEXT40(MAX32))
	tmp = (MAX32);
      else if (tmp < SEXT40(MIN32))
	tmp = (MIN32);
      else
	tmp = (tmp & MASK40);
    }
  else
    tmp = (tmp & MASK40);
  SET_ACC (OP[0], tmp);

  trace_output_40 (tmp);
}

/* sub2w */
void
OP_1000 ()
{
  uint32 tmp, a, b;

  trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
  a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
  b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
  /* see ../common/sim-alu.h for a more extensive discussion on how to
     compute the carry/overflow bits */
  tmp = a - b;
  SET_PSW_C (a >= b);
  SET_GPR32 (OP[0], tmp);
  trace_output_32 (tmp);
}

/* subac3 */
void
OP_17000000 ()
{
  int64 tmp;

  trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
  tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
  SET_GPR32 (OP[0], tmp);
  trace_output_32 (tmp);
}

/* subac3 */
void
OP_17000002 ()
{
  int64 tmp;

  trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
  tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
  SET_GPR32 (OP[0], tmp);
  trace_output_32 (tmp);
}

/* subac3s */
void
OP_17001000 ()
{
  int64 tmp;

  trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
  SET_PSW_F1 (PSW_F0);
  tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
  if (tmp > SEXT40(MAX32))
    {
      tmp = (MAX32);
      SET_PSW_F0 (1);
    }      
  else if (tmp < SEXT40(MIN32))
    {
      tmp = (MIN32);
      SET_PSW_F0 (1);
    }      
  else
    {
      SET_PSW_F0 (0);
    }      
  SET_GPR32 (OP[0], tmp);
  trace_output_32 (tmp);
}

/* subac3s */
void
OP_17001002 ()
{
  int64 tmp;

  trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
  SET_PSW_F1 (PSW_F0);
  tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
  if (tmp > SEXT40(MAX32))
    {
      tmp = (MAX32);
      SET_PSW_F0 (1);
    }      
  else if (tmp < SEXT40(MIN32))
    {
      tmp = (MIN32);
      SET_PSW_F0 (1);
    }      
  else
    {
      SET_PSW_F0 (0);
    }      
  SET_GPR32 (OP[0], tmp);
  trace_output_32 (tmp);
}

/* subi */
void
OP_1 ()
{
  unsigned tmp;
  if (OP[1] == 0)
    OP[1] = 16;

  trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
  /* see ../common/sim-alu.h for a more extensive discussion on how to
     compute the carry/overflow bits. */
  /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
  tmp = ((unsigned)(unsigned16) GPR (OP[0])
	 + (unsigned)(unsigned16) ( - OP[1]));
  SET_PSW_C (tmp >= (1 << 16));
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* trap */
void
OP_5F00 ()
{
  trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
  trace_output_void ();

  switch (OP[0])
    {
    default:
#if (DEBUG & DEBUG_TRAP) == 0
      {
	uint16 vec = OP[0] + TRAP_VECTOR_START;
	SET_BPC (PC + 1);
	SET_BPSW (PSW);
	SET_PSW (PSW & PSW_SM_BIT);
	JMP (vec);
	break;
      }
#else			/* if debugging use trap to print registers */
      {
	int i;
	static int first_time = 1;

	if (first_time)
	  {
	    first_time = 0;
	    (*d10v_callback->printf_filtered) (d10v_callback, "Trap  #     PC ");
	    for (i = 0; i < 16; i++)
	      (*d10v_callback->printf_filtered) (d10v_callback, "  %sr%d", (i > 9) ? "" : " ", i);
	    (*d10v_callback->printf_filtered) (d10v_callback, "         a0         a1 f0 f1 c\n");
	  }

	(*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);

	for (i = 0; i < 16; i++)
	  (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));

	for (i = 0; i < 2; i++)
	  (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
					     ((int)(ACC (i) >> 32) & 0xff),
					     ((unsigned long) ACC (i)) & 0xffffffff);

	(*d10v_callback->printf_filtered) (d10v_callback, "  %d  %d %d\n",
					   PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
	(*d10v_callback->flush_stdout) (d10v_callback);
	break;
      }
#endif
    case 15:			/* new system call trap */
      /* Trap 15 is used for simulating low-level I/O */
      {
	unsigned32 result = 0;
	errno = 0;

/* Registers passed to trap 0 */

#define FUNC   GPR (4)	/* function number */
#define PARM1  GPR (0)	/* optional parm 1 */
#define PARM2  GPR (1)	/* optional parm 2 */
#define PARM3  GPR (2)	/* optional parm 3 */
#define PARM4  GPR (3)	/* optional parm 3 */

/* Registers set by trap 0 */

#define RETVAL(X)   do { result = (X); SET_GPR (0, result); } while (0)
#define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
#define RETERR(X) SET_GPR (4, (X))		/* return error code */

/* Turn a pointer in a register into a pointer into real memory. */

#define MEMPTR(x) ((char *)(dmem_addr(x)))

	switch (FUNC)
	  {
#if !defined(__GO32__) && !defined(_WIN32)
	  case TARGET_SYS_fork:
	    trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
	    RETVAL (fork ());
	    trace_output_16 (result);
	    break;

#define getpid() 47
	  case TARGET_SYS_getpid:
	    trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
	    RETVAL (getpid ());
	    trace_output_16 (result);
	    break;

	  case TARGET_SYS_kill:
	    trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
	    if (PARM1 == getpid ())
	      {
		trace_output_void ();
		State.exception = PARM2;
	      }
	    else
	      {
		int os_sig = -1;
		switch (PARM2)
		  {
#ifdef SIGHUP
		  case 1: os_sig = SIGHUP;	break;
#endif
#ifdef SIGINT
		  case 2: os_sig = SIGINT;	break;
#endif
#ifdef SIGQUIT
		  case 3: os_sig = SIGQUIT;	break;
#endif
#ifdef SIGILL
		  case 4: os_sig = SIGILL;	break;
#endif
#ifdef SIGTRAP
		  case 5: os_sig = SIGTRAP;	break;
#endif
#ifdef SIGABRT
		  case 6: os_sig = SIGABRT;	break;
#elif defined(SIGIOT)
		  case 6: os_sig = SIGIOT;	break;
#endif
#ifdef SIGEMT
		  case 7: os_sig = SIGEMT;	break;
#endif
#ifdef SIGFPE
		  case 8: os_sig = SIGFPE;	break;
#endif
#ifdef SIGKILL
		  case 9: os_sig = SIGKILL;	break;
#endif
#ifdef SIGBUS
		  case 10: os_sig = SIGBUS;	break;
#endif
#ifdef SIGSEGV
		  case 11: os_sig = SIGSEGV;	break;
#endif
#ifdef SIGSYS
		  case 12: os_sig = SIGSYS;	break;
#endif
#ifdef SIGPIPE
		  case 13: os_sig = SIGPIPE;	break;
#endif
#ifdef SIGALRM
		  case 14: os_sig = SIGALRM;	break;
#endif
#ifdef SIGTERM
		  case 15: os_sig = SIGTERM;	break;
#endif
#ifdef SIGURG
		  case 16: os_sig = SIGURG;	break;
#endif
#ifdef SIGSTOP
		  case 17: os_sig = SIGSTOP;	break;
#endif
#ifdef SIGTSTP
		  case 18: os_sig = SIGTSTP;	break;
#endif
#ifdef SIGCONT
		  case 19: os_sig = SIGCONT;	break;
#endif
#ifdef SIGCHLD
		  case 20: os_sig = SIGCHLD;	break;
#elif defined(SIGCLD)
		  case 20: os_sig = SIGCLD;	break;
#endif
#ifdef SIGTTIN
		  case 21: os_sig = SIGTTIN;	break;
#endif
#ifdef SIGTTOU
		  case 22: os_sig = SIGTTOU;	break;
#endif
#ifdef SIGIO
		  case 23: os_sig = SIGIO;	break;
#elif defined (SIGPOLL)
		  case 23: os_sig = SIGPOLL;	break;
#endif
#ifdef SIGXCPU
		  case 24: os_sig = SIGXCPU;	break;
#endif
#ifdef SIGXFSZ
		  case 25: os_sig = SIGXFSZ;	break;
#endif
#ifdef SIGVTALRM
		  case 26: os_sig = SIGVTALRM;	break;
#endif
#ifdef SIGPROF
		  case 27: os_sig = SIGPROF;	break;
#endif
#ifdef SIGWINCH
		  case 28: os_sig = SIGWINCH;	break;
#endif
#ifdef SIGLOST
		  case 29: os_sig = SIGLOST;	break;
#endif
#ifdef SIGUSR1
		  case 30: os_sig = SIGUSR1;	break;
#endif
#ifdef SIGUSR2
		  case 31: os_sig = SIGUSR2;	brea