simops.c

这个是LINUX下的GDB调度工具的源码

  trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
  tmp = ACC (OP[1]);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* mvfc */
void
OP_5200 ()
{
  int16 tmp;
  trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
  tmp = CREG (OP[1]);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* mvtacg */
void
OP_1E41 ()
{
  int64 tmp;
  trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
  tmp = ((ACC (OP[1]) & MASK32)
	 | ((int64)(GPR (OP[0]) & 0xff) << 32));
  SET_ACC (OP[1], tmp);
  trace_output_40 (tmp);
}

/* mvtachi */
void
OP_1E01 ()
{
  uint64 tmp;
  trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
  tmp = ACC (OP[1]) & 0xffff;
  tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
  SET_ACC (OP[1], tmp);
  trace_output_40 (tmp);
}

/* mvtaclo */
void
OP_1E21 ()
{
  int64 tmp;
  trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
  tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
  SET_ACC (OP[1], tmp);
  trace_output_40 (tmp);
}

/* mvtc */
void
OP_5600 ()
{
  int16 tmp;
  trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
  tmp = GPR (OP[0]);
  tmp = SET_CREG (OP[1], tmp);
  trace_output_16 (tmp);
}

/* mvub */
void
OP_5401 ()
{
  int16 tmp;
  trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
  tmp = (GPR (OP[1]) & 0xff);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* neg */
void
OP_4605 ()
{
  int16 tmp;
  trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
  tmp = - GPR (OP[0]);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* neg */
void
OP_5605 ()
{
  int64 tmp;

  trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
  tmp = -SEXT40(ACC (OP[0]));
  if (PSW_ST)
    {
      if (tmp > SEXT40(MAX32))
	tmp = (MAX32);
      else if (tmp < SEXT40(MIN32))
	tmp = (MIN32);
      else
	tmp = (tmp & MASK40);
    }
  else
    tmp = (tmp & MASK40);
  SET_ACC (OP[0], tmp);
  trace_output_40 (tmp);
}


/* nop */
void
OP_5E00 ()
{
  trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);

  ins_type_counters[ (int)State.ins_type ]--;	/* don't count nops as normal instructions */
  switch (State.ins_type)
    {
    default:
      ins_type_counters[ (int)INS_UNKNOWN ]++;
      break;

    case INS_LEFT_PARALLEL:
      /* Don't count a parallel op that includes a NOP as a true parallel op */
      ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
      ins_type_counters[ (int)INS_RIGHT ]++;
      ins_type_counters[ (int)INS_LEFT_NOPS ]++;
      break;

    case INS_LEFT:
    case INS_LEFT_COND_EXE:
      ins_type_counters[ (int)INS_LEFT_NOPS ]++;
      break;

    case INS_RIGHT_PARALLEL:
      /* Don't count a parallel op that includes a NOP as a true parallel op */
      ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
      ins_type_counters[ (int)INS_LEFT ]++;
      ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
      break;

    case INS_RIGHT:
    case INS_RIGHT_COND_EXE:
      ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
      break;
    }

  trace_output_void ();
}

/* not */
void
OP_4603 ()
{
  int16 tmp;
  trace_input ("not", OP_REG, OP_VOID, OP_VOID);
  tmp = ~GPR (OP[0]);  
  SET_GPR (OP[0], tmp);  
  trace_output_16 (tmp);
}

/* or */
void
OP_800 ()
{
  int16 tmp;
  trace_input ("or", OP_REG, OP_REG, OP_VOID);
  tmp = (GPR (OP[0]) | GPR (OP[1]));
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* or3 */
void
OP_4000000 ()
{
  int16 tmp;
  trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
  tmp = (GPR (OP[1]) | OP[2]);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* rac */
void
OP_5201 ()
{
  int64 tmp;
  int shift = SEXT3 (OP[2]);

  trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
  if (OP[1] != 0)
    {
      (*d10v_callback->printf_filtered) (d10v_callback,
					 "ERROR at PC 0x%x: instruction only valid for A0\n",
					 PC<<2);
      State.exception = SIGILL;
    }

  SET_PSW_F1 (PSW_F0);
  tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
  if (shift >=0)
    tmp <<= shift;
  else
    tmp >>= -shift;
  tmp += 0x8000;
  tmp >>= 16; /* look at bits 0:43 */
  if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
    {
      tmp = 0x7fffffff;
      SET_PSW_F0 (1);
    } 
  else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
    {
      tmp = 0x80000000;
      SET_PSW_F0 (1);
    } 
  else
    {
      SET_PSW_F0 (0);
    }
  SET_GPR32 (OP[0], tmp);
  trace_output_32 (tmp);
}

/* rachi */
void
OP_4201 ()
{
  signed64 tmp;
  int shift = SEXT3 (OP[2]);

  trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
  SET_PSW_F1 (PSW_F0);
  if (shift >=0)
    tmp = SEXT40 (ACC (OP[1])) << shift;
  else
    tmp = SEXT40 (ACC (OP[1])) >> -shift;
  tmp += 0x8000;

  if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
    {
      tmp = 0x7fff;
      SET_PSW_F0 (1);
    }
  else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
    {
      tmp = 0x8000;
      SET_PSW_F0 (1);
    }
  else
    {
      tmp = (tmp >> 16);
      SET_PSW_F0 (0);
    }
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* rep */
void
OP_27000000 ()
{
  trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
  SET_RPT_S (PC + 1);
  SET_RPT_E (PC + OP[1]);
  SET_RPT_C (GPR (OP[0]));
  SET_PSW_RP (1);
  if (GPR (OP[0]) == 0)
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
      State.exception = SIGILL;
    }
  if (OP[1] < 4)
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
      State.exception = SIGILL;
    }
  trace_output_void ();
}

/* repi */
void
OP_2F000000 ()
{
  trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
  SET_RPT_S (PC + 1);
  SET_RPT_E (PC + OP[1]);
  SET_RPT_C (OP[0]);
  SET_PSW_RP (1);
  if (OP[0] == 0)
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
      State.exception = SIGILL;
    }
  if (OP[1] < 4)
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
      State.exception = SIGILL;
    }
  trace_output_void ();
}

/* rtd */
void
OP_5F60 ()
{
  trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
  SET_CREG (PSW_CR, DPSW);
  JMP(DPC);
  trace_output_void ();
}

/* rte */
void
OP_5F40 ()
{
  trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
  SET_CREG (PSW_CR, BPSW);
  JMP(BPC);
  trace_output_void ();
}

/* sac */
void OP_5209 ()
{
  int64 tmp;

  trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);

  tmp = SEXT40(ACC (OP[1]));

  SET_PSW_F1 (PSW_F0);

  if (tmp > SEXT40(MAX32))
    {
      tmp = (MAX32);
      SET_PSW_F0 (1);
    }
  else if (tmp < SEXT40(MIN32))
    {
      tmp = 0x80000000;
      SET_PSW_F0 (1);
    }
  else
    {
      tmp = (tmp & MASK32);
      SET_PSW_F0 (0);
    }

  SET_GPR32 (OP[0], tmp);

  trace_output_40 (tmp);
}

/* sachi */
void
OP_4209 ()
{
  int64 tmp;

  trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);

  tmp = SEXT40(ACC (OP[1]));

  SET_PSW_F1 (PSW_F0);

  if (tmp > SEXT40(MAX32))
    {
      tmp = 0x7fff;
      SET_PSW_F0 (1);
    }
  else if (tmp < SEXT40(MIN32))
    {
      tmp = 0x8000;
      SET_PSW_F0 (1);
    }
  else
    {
      tmp >>= 16;
      SET_PSW_F0 (0);
    }

  SET_GPR (OP[0], tmp);

  trace_output_16 (OP[0]);
}

/* sadd */
void
OP_1223 ()
{
  int64 tmp;

  trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
  tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
  if (PSW_ST)
    {
      if (tmp > SEXT40(MAX32))
	tmp = (MAX32);
      else if (tmp < SEXT40(MIN32))
	tmp = (MIN32);
      else
	tmp = (tmp & MASK40);
    }
  else
    tmp = (tmp & MASK40);
  SET_ACC (OP[0], tmp);
  trace_output_40 (tmp);
}

/* setf0f */
void
OP_4611 ()
{
  int16 tmp;
  trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
  tmp = ((PSW_F0 == 0) ? 1 : 0);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* setf0t */
void
OP_4613 ()
{
  int16 tmp;
  trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
  tmp = ((PSW_F0 == 1) ? 1 : 0);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* slae */
void
OP_3220 ()
{
  int64 tmp;
  int16 reg;

  trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);

  reg = SEXT16 (GPR (OP[1]));

  if (reg >= 17 || reg <= -17)
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
      State.exception = SIGILL;
      return;
    }

  tmp = SEXT40 (ACC (OP[0]));

  if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
      State.exception = SIGILL;
      return;
    }

  if (reg >= 0 && reg <= 16)
    {
      tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
      if (PSW_ST)
	{
	  if (tmp > SEXT40(MAX32))
	    tmp = (MAX32);
	  else if (tmp < SEXT40(MIN32))
	    tmp = (MIN32);
	  else
	    tmp = (tmp & MASK40);
	}
      else
	tmp = (tmp & MASK40);
    }
  else
    {
      tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
    }

  SET_ACC(OP[0], tmp);

  trace_output_40(tmp);
}

/* sleep */
void
OP_5FC0 ()
{
  trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
  SET_PSW_IE (1);
  trace_output_void ();
}

/* sll */
void
OP_2200 ()
{
  int16 tmp;
  trace_input ("sll", OP_REG, OP_REG, OP_VOID);
  tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* sll */
void
OP_3200 ()
{
  int64 tmp;
  trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
  if ((GPR (OP[1]) & 31) <= 16)
    tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
  else
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
      State.exception = SIGILL;
      return;
    }

  if (PSW_ST)
    {
      if (tmp > SEXT40(MAX32))
	tmp = (MAX32);
      else if (tmp < SEXT40(MIN32))
	tmp = (MIN32);
      else
	tmp = (tmp & MASK40);
    }
  else
    tmp = (tmp & MASK40);
  SET_ACC (OP[0], tmp);
  trace_output_40 (tmp);
}

/* slli */
void
OP_2201 ()
{
  int16 tmp;
  trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
  tmp = (GPR (OP[0]) << OP[1]);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* slli */
void
OP_3201 ()
{
  int64 tmp;

  if (OP[1] == 0)
    OP[1] = 16;

  trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
  tmp = SEXT40(ACC (OP[0])) << OP[1];

  if (PSW_ST)
    {
      if (tmp > SEXT40(MAX32))
	tmp = (MAX32);
      else if (tmp < SEXT40(MIN32))
	tmp = (MIN32);
      else
	tmp = (tmp & MASK40);
    }
  else
    tmp = (tmp & MASK40);
  SET_ACC (OP[0], tmp);
  trace_output_40 (tmp);
}

/* slx */
void
OP_460B ()
{
  int16 tmp;
  trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
  tmp = ((GPR (OP[0]) << 1) | PSW_F0);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* sra */
void
OP_2400 ()
{
  int16 tmp;
  trace_input ("sra", OP_REG, OP_REG, OP_VOID);
  tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* sra */
void
OP_3400 ()
{
  trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
  if ((GPR (OP[1]) & 31) <= 16)
    {
      int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
      SET_ACC (OP[0], tmp);
      trace_output_40 (tmp);
    }
  else
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
      State.exception = SIGILL;
      return;
    }
}

/* srai */
void
OP_2401 ()
{
  int16 tmp;
  trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
  tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* srai */
void
OP_3401 ()
{
  int64 tmp;
  if (OP[1] == 0)
    OP[1] = 16;

  trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
  tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
  SET_ACC (OP[0], tmp);
  trace_output_40 (tmp);
}

/* srl */
void
OP_2000 ()
{
  int16 tmp;
  trace_input ("srl", OP_REG, OP_REG, OP_VOID);
  tmp = (GPR (OP[0]) >>  (GPR (OP[1]) & 0xf));
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* srl */
void
OP_3000 ()
{
  trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
  if ((GPR (OP[1]) & 31) <= 16)
    {
      int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
      SET_ACC (OP[0], tmp);
      trace_output_40 (tmp);
    }
  else
    {
      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
      State.exception = SIGILL;
      return;
    }

}

/* srli */
void
OP_2001 ()
{
  int16 tmp;
  trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
  tmp = (GPR (OP[0]) >> OP[1]);