simops.c

这个是LINUX下的GDB调度工具的源码

  trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
  if (PSW_ST)
    {
      if (tmp > SEXT40(MAX32))
	tmp = (MAX32);
      else if (tmp < SEXT40(MIN32))
	tmp = (MIN32);
      else
	tmp = (tmp & MASK40);
    }
  else
    tmp = (tmp & MASK40);
  SET_ACC (OP[0], tmp);
  trace_output_40 (tmp);
}

/* add2w */
void
OP_1200 ()
{
  uint32 tmp;
  uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
  uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
  trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
  tmp = a + b;
  SET_PSW_C (tmp < a);
  SET_GPR (OP[0] + 0, (tmp >> 16));
  SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
  trace_output_32 (tmp);
}

/* add3 */
void
OP_1000000 ()
{
  uint16 a = GPR (OP[1]);
  uint16 b = OP[2];
  uint16 tmp = (a + b);
  trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
  SET_PSW_C (tmp < a);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* addac3 */
void
OP_17000200 ()
{
  int64 tmp;
  tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));

  trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
  SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
  SET_GPR (OP[0] + 1, (tmp & 0xffff));
  trace_output_32 (tmp);
}

/* addac3 */
void
OP_17000202 ()
{
  int64 tmp;
  tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));

  trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
  SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
  SET_GPR (OP[0] + 1, tmp & 0xffff);
  trace_output_32 (tmp);
}

/* addac3s */
void
OP_17001200 ()
{
  int64 tmp;
  SET_PSW_F1 (PSW_F0);

  trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
  tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
  if (tmp > SEXT40(MAX32))
    {
      tmp = (MAX32);
      SET_PSW_F0 (1);
    }      
  else if (tmp < SEXT40(MIN32))
    {
      tmp = (MIN32);
      SET_PSW_F0 (1);
    }      
  else
    {
      SET_PSW_F0 (0);
    }      
  SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
  SET_GPR (OP[0] + 1, (tmp & 0xffff));
  trace_output_32 (tmp);
}

/* addac3s */
void
OP_17001202 ()
{
  int64 tmp;
  SET_PSW_F1 (PSW_F0);

  trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
  tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
  if (tmp > SEXT40(MAX32))
    {
      tmp = (MAX32);
      SET_PSW_F0 (1);
    }      
  else if (tmp < SEXT40(MIN32))
    {
      tmp = (MIN32);
      SET_PSW_F0 (1);
    }      
  else
    {
      SET_PSW_F0 (0);
    }      
  SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
  SET_GPR (OP[0] + 1, (tmp & 0xffff));
  trace_output_32 (tmp);
}

/* addi */
void
OP_201 ()
{
  uint16 a = GPR (OP[0]);
  uint16 b;
  uint16 tmp;
  if (OP[1] == 0)
    OP[1] = 16;
  b = OP[1];
  tmp = (a + b);
  trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
  SET_PSW_C (tmp < a);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* and */
void
OP_C00 ()
{
  uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
  trace_input ("and", OP_REG, OP_REG, OP_VOID);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* and3 */
void
OP_6000000 ()
{
  uint16 tmp = GPR (OP[1]) & OP[2];
  trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* bclri */
void
OP_C01 ()
{
  int16 tmp;
  trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
  tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* bl.s */
void
OP_4900 ()
{
  trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
  SET_GPR (13, PC + 1);
  JMP( PC + SEXT8 (OP[0]));
  trace_output_void ();
}

/* bl.l */
void
OP_24800000 ()
{
  trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
  SET_GPR (13, (PC + 1));
  JMP (PC + OP[0]);
  trace_output_void ();
}

/* bnoti */
void
OP_A01 ()
{
  int16 tmp;
  trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
  tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* bra.s */
void
OP_4800 ()
{
  trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
  JMP (PC + SEXT8 (OP[0]));
  trace_output_void ();
}

/* bra.l */
void
OP_24000000 ()
{
  trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
  JMP (PC + OP[0]);
  trace_output_void ();
}

/* brf0f.s */
void
OP_4A00 ()
{
  trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
  if (!PSW_F0)
    JMP (PC + SEXT8 (OP[0]));
  trace_output_flag ();
}

/* brf0f.l */
void
OP_25000000 ()
{
  trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
  if (!PSW_F0)
    JMP (PC + OP[0]);
  trace_output_flag ();
}

/* brf0t.s */
void
OP_4B00 ()
{
  trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
  if (PSW_F0)
    JMP (PC + SEXT8 (OP[0]));
  trace_output_flag ();
}

/* brf0t.l */
void
OP_25800000 ()
{
  trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
  if (PSW_F0)
    JMP (PC + OP[0]);
  trace_output_flag ();
}

/* bseti */
void
OP_801 ()
{
  int16 tmp;
  trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
  tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* btsti */
void
OP_E01 ()
{
  trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
  trace_output_flag ();
}

/* clrac */
void
OP_5601 ()
{
  trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
  SET_ACC (OP[0], 0);
  trace_output_40 (0);
}

/* cmp */
void
OP_600 ()
{
  trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
  trace_output_flag ();
}

/* cmp */
void
OP_1603 ()
{
  trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
  trace_output_flag ();
}

/* cmpeq */
void
OP_400 ()
{
  trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
  trace_output_flag ();
}

/* cmpeq */
void
OP_1403 ()
{
  trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
  trace_output_flag ();
}

/* cmpeqi.s */
void
OP_401 ()
{
  trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);  
  trace_output_flag ();
}

/* cmpeqi.l */
void
OP_2000000 ()
{
  trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);  
  trace_output_flag ();
}

/* cmpi.s */
void
OP_601 ()
{
  trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);  
  trace_output_flag ();
}

/* cmpi.l */
void
OP_3000000 ()
{
  trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);  
  trace_output_flag ();
}

/* cmpu */
void
OP_4600 ()
{
  trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);  
  trace_output_flag ();
}

/* cmpui */
void
OP_23000000 ()
{
  trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
  SET_PSW_F1 (PSW_F0);
  SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);  
  trace_output_flag ();
}

/* cpfg */
void
OP_4E09 ()
{
  uint8 val;
  
  trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
  
  if (OP[1] == 0)
    val = PSW_F0;
  else if (OP[1] == 1)
    val = PSW_F1;
  else
    val = PSW_C;
  if (OP[0] == 0)
    SET_PSW_F0 (val);
  else
    SET_PSW_F1 (val);

  trace_output_flag ();
}

/* cpfg */
void
OP_4E0F ()
{
  uint8 val;
  
  trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
  
  if (OP[1] == 0)
    val = PSW_F0;
  else if (OP[1] == 1)
    val = PSW_F1;
  else
    val = PSW_C;
  if (OP[0] == 0)
    SET_PSW_F0 (val);
  else
    SET_PSW_F1 (val);

  trace_output_flag ();
}

/* dbt */
void
OP_5F20 ()
{
  /* d10v_callback->printf_filtered(d10v_callback, "***** DBT *****  PC=%x\n",PC); */

  /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
     The conditional below is for either of the instruction pairs
     ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
     where the dbt instruction should be interpreted.

     The module `sim-break' provides a more effective mechanism for
     detecting GDB planted breakpoints.  The code below may,
     eventually, be changed to use that mechanism. */

  if (State.ins_type == INS_LEFT
      || State.ins_type == INS_RIGHT)
    {
      trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
      SET_DPC (PC + 1);
      SET_DPSW (PSW);
      SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
      JMP (DBT_VECTOR_START);
      trace_output_void ();
    }
  else
    {
      State.exception = SIGTRAP;
    }
}

/* divs */
void
OP_14002800 ()
{
  uint16 foo, tmp, tmpf;
  uint16 hi;
  uint16 lo;

  trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
  foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
  tmp = (int16)foo - (int16)(GPR (OP[1]));
  tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
  hi = ((tmpf == 1) ? tmp : foo);
  lo = ((GPR (OP[0] + 1) << 1) | tmpf);
  SET_GPR (OP[0] + 0, hi);
  SET_GPR (OP[0] + 1, lo);
  trace_output_32 (((uint32) hi << 16) | lo);
}

/* exef0f */
void
OP_4E04 ()
{
  trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
  State.exe = (PSW_F0 == 0);
  trace_output_flag ();
}

/* exef0t */
void
OP_4E24 ()
{
  trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
  State.exe = (PSW_F0 != 0);
  trace_output_flag ();
}

/* exef1f */
void
OP_4E40 ()
{
  trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
  State.exe = (PSW_F1 == 0);
  trace_output_flag ();
}

/* exef1t */
void
OP_4E42 ()
{
  trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
  State.exe = (PSW_F1 != 0);
  trace_output_flag ();
}

/* exefaf */
void
OP_4E00 ()
{
  trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
  State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
  trace_output_flag ();
}

/* exefat */
void
OP_4E02 ()
{
  trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
  State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
  trace_output_flag ();
}

/* exetaf */
void
OP_4E20 ()
{
  trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
  State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
  trace_output_flag ();
}

/* exetat */
void
OP_4E22 ()
{
  trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
  State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
  trace_output_flag ();
}

/* exp */
void
OP_15002A00 ()
{
  uint32 tmp, foo;
  int i;

  trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
  if (((int16)GPR (OP[1])) >= 0)
    tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
  else
    tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
  
  foo = 0x40000000;
  for (i=1;i<17;i++)
    {
      if (tmp & foo)
	{
	  SET_GPR (OP[0], (i - 1));
	  trace_output_16 (i - 1);
	  return;
	}
      foo >>= 1;
    }
  SET_GPR (OP[0], 16);
  trace_output_16 (16);
}

/* exp */
void
OP_15002A02 ()
{
  int64 tmp, foo;
  int i;

  trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
  tmp = SEXT40(ACC (OP[1]));
  if (tmp < 0)
    tmp = ~tmp & MASK40;
  
  foo = 0x4000000000LL;
  for (i=1;i<25;i++)
    {
      if (tmp & foo)
	{
	  SET_GPR (OP[0], i - 9);
	  trace_output_16 (i - 9);
	  return;
	}
      foo >>= 1;
    }
  SET_GPR (OP[0], 16);
  trace_output_16 (16);
}

/* jl */
void
OP_4D00 ()
{
  trace_input ("jl", OP_REG, OP_R0, OP_R1);
  SET_GPR (13, PC + 1);
  JMP (GPR (OP[0]));
  trace_output_void ();
}

/* jmp */
void
OP_4C00 ()
{
  trace_input ("jmp", OP_REG,
	       (OP[0] == 13) ? OP_R0 : OP_VOID,
	       (OP[0] == 13) ? OP_R1 : OP_VOID);

  JMP (GPR (OP[0]));
  trace_output_void ();
}

/* ld */
void
OP_30000000 ()
{
  uint16 tmp;
  uint16 addr = OP[1] + GPR (OP[2]);
  trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  tmp = RW (addr);
  SET_GPR (OP[0], tmp);
  trace_output_16 (tmp);
}

/* ld */
void
OP_6401 ()
{
  uint16 tmp;
  uint16 addr = GPR (OP[1]);
  trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
  if ((addr & 1))
    {
      State.exception = SIG_D10V_BUS;
      State.pc_changed = 1; /* Don't increment the PC. */
      trace_output_void ();
      return;
    }
  tmp = RW (addr);
  SET_GPR (OP[0], tmp);
  if (OP[0] != OP[1])
    INC_ADDR (OP[1], -2);
  trace_output_16 (tmp);
}

/* ld */