decode.c

这个是LINUX下的GDB调度工具的源码

  { I960_INSN_STL_INDIRECT_OFFSET, I960BASE_INSN_STL_INDIRECT_OFFSET, I960BASE_SFMT_STL_INDIRECT_OFFSET },
  { I960_INSN_STL_INDIRECT, I960BASE_INSN_STL_INDIRECT, I960BASE_SFMT_STL_INDIRECT },
  { I960_INSN_STL_INDIRECT_INDEX, I960BASE_INSN_STL_INDIRECT_INDEX, I960BASE_SFMT_STL_INDIRECT_INDEX },
  { I960_INSN_STL_DISP, I960BASE_INSN_STL_DISP, I960BASE_SFMT_STL_DISP },
  { I960_INSN_STL_INDIRECT_DISP, I960BASE_INSN_STL_INDIRECT_DISP, I960BASE_SFMT_STL_INDIRECT_DISP },
  { I960_INSN_STL_INDEX_DISP, I960BASE_INSN_STL_INDEX_DISP, I960BASE_SFMT_STL_INDEX_DISP },
  { I960_INSN_STL_INDIRECT_INDEX_DISP, I960BASE_INSN_STL_INDIRECT_INDEX_DISP, I960BASE_SFMT_STL_INDIRECT_INDEX_DISP },
  { I960_INSN_STT_OFFSET, I960BASE_INSN_STT_OFFSET, I960BASE_SFMT_STT_OFFSET },
  { I960_INSN_STT_INDIRECT_OFFSET, I960BASE_INSN_STT_INDIRECT_OFFSET, I960BASE_SFMT_STT_INDIRECT_OFFSET },
  { I960_INSN_STT_INDIRECT, I960BASE_INSN_STT_INDIRECT, I960BASE_SFMT_STT_INDIRECT },
  { I960_INSN_STT_INDIRECT_INDEX, I960BASE_INSN_STT_INDIRECT_INDEX, I960BASE_SFMT_STT_INDIRECT_INDEX },
  { I960_INSN_STT_DISP, I960BASE_INSN_STT_DISP, I960BASE_SFMT_STT_DISP },
  { I960_INSN_STT_INDIRECT_DISP, I960BASE_INSN_STT_INDIRECT_DISP, I960BASE_SFMT_STT_INDIRECT_DISP },
  { I960_INSN_STT_INDEX_DISP, I960BASE_INSN_STT_INDEX_DISP, I960BASE_SFMT_STT_INDEX_DISP },
  { I960_INSN_STT_INDIRECT_INDEX_DISP, I960BASE_INSN_STT_INDIRECT_INDEX_DISP, I960BASE_SFMT_STT_INDIRECT_INDEX_DISP },
  { I960_INSN_STQ_OFFSET, I960BASE_INSN_STQ_OFFSET, I960BASE_SFMT_STQ_OFFSET },
  { I960_INSN_STQ_INDIRECT_OFFSET, I960BASE_INSN_STQ_INDIRECT_OFFSET, I960BASE_SFMT_STQ_INDIRECT_OFFSET },
  { I960_INSN_STQ_INDIRECT, I960BASE_INSN_STQ_INDIRECT, I960BASE_SFMT_STQ_INDIRECT },
  { I960_INSN_STQ_INDIRECT_INDEX, I960BASE_INSN_STQ_INDIRECT_INDEX, I960BASE_SFMT_STQ_INDIRECT_INDEX },
  { I960_INSN_STQ_DISP, I960BASE_INSN_STQ_DISP, I960BASE_SFMT_STQ_DISP },
  { I960_INSN_STQ_INDIRECT_DISP, I960BASE_INSN_STQ_INDIRECT_DISP, I960BASE_SFMT_STQ_INDIRECT_DISP },
  { I960_INSN_STQ_INDEX_DISP, I960BASE_INSN_STQ_INDEX_DISP, I960BASE_SFMT_STQ_INDEX_DISP },
  { I960_INSN_STQ_INDIRECT_INDEX_DISP, I960BASE_INSN_STQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_STQ_INDIRECT_INDEX_DISP },
  { I960_INSN_CMPOBE_REG, I960BASE_INSN_CMPOBE_REG, I960BASE_SFMT_CMPOBE_REG },
  { I960_INSN_CMPOBE_LIT, I960BASE_INSN_CMPOBE_LIT, I960BASE_SFMT_CMPOBE_LIT },
  { I960_INSN_CMPOBNE_REG, I960BASE_INSN_CMPOBNE_REG, I960BASE_SFMT_CMPOBE_REG },
  { I960_INSN_CMPOBNE_LIT, I960BASE_INSN_CMPOBNE_LIT, I960BASE_SFMT_CMPOBE_LIT },
  { I960_INSN_CMPOBL_REG, I960BASE_INSN_CMPOBL_REG, I960BASE_SFMT_CMPOBL_REG },
  { I960_INSN_CMPOBL_LIT, I960BASE_INSN_CMPOBL_LIT, I960BASE_SFMT_CMPOBL_LIT },
  { I960_INSN_CMPOBLE_REG, I960BASE_INSN_CMPOBLE_REG, I960BASE_SFMT_CMPOBL_REG },
  { I960_INSN_CMPOBLE_LIT, I960BASE_INSN_CMPOBLE_LIT, I960BASE_SFMT_CMPOBL_LIT },
  { I960_INSN_CMPOBG_REG, I960BASE_INSN_CMPOBG_REG, I960BASE_SFMT_CMPOBL_REG },
  { I960_INSN_CMPOBG_LIT, I960BASE_INSN_CMPOBG_LIT, I960BASE_SFMT_CMPOBL_LIT },
  { I960_INSN_CMPOBGE_REG, I960BASE_INSN_CMPOBGE_REG, I960BASE_SFMT_CMPOBL_REG },
  { I960_INSN_CMPOBGE_LIT, I960BASE_INSN_CMPOBGE_LIT, I960BASE_SFMT_CMPOBL_LIT },
  { I960_INSN_CMPIBE_REG, I960BASE_INSN_CMPIBE_REG, I960BASE_SFMT_CMPOBE_REG },
  { I960_INSN_CMPIBE_LIT, I960BASE_INSN_CMPIBE_LIT, I960BASE_SFMT_CMPOBE_LIT },
  { I960_INSN_CMPIBNE_REG, I960BASE_INSN_CMPIBNE_REG, I960BASE_SFMT_CMPOBE_REG },
  { I960_INSN_CMPIBNE_LIT, I960BASE_INSN_CMPIBNE_LIT, I960BASE_SFMT_CMPOBE_LIT },
  { I960_INSN_CMPIBL_REG, I960BASE_INSN_CMPIBL_REG, I960BASE_SFMT_CMPOBE_REG },
  { I960_INSN_CMPIBL_LIT, I960BASE_INSN_CMPIBL_LIT, I960BASE_SFMT_CMPOBE_LIT },
  { I960_INSN_CMPIBLE_REG, I960BASE_INSN_CMPIBLE_REG, I960BASE_SFMT_CMPOBE_REG },
  { I960_INSN_CMPIBLE_LIT, I960BASE_INSN_CMPIBLE_LIT, I960BASE_SFMT_CMPOBE_LIT },
  { I960_INSN_CMPIBG_REG, I960BASE_INSN_CMPIBG_REG, I960BASE_SFMT_CMPOBE_REG },
  { I960_INSN_CMPIBG_LIT, I960BASE_INSN_CMPIBG_LIT, I960BASE_SFMT_CMPOBE_LIT },
  { I960_INSN_CMPIBGE_REG, I960BASE_INSN_CMPIBGE_REG, I960BASE_SFMT_CMPOBE_REG },
  { I960_INSN_CMPIBGE_LIT, I960BASE_INSN_CMPIBGE_LIT, I960BASE_SFMT_CMPOBE_LIT },
  { I960_INSN_BBC_REG, I960BASE_INSN_BBC_REG, I960BASE_SFMT_BBC_REG },
  { I960_INSN_BBC_LIT, I960BASE_INSN_BBC_LIT, I960BASE_SFMT_BBC_LIT },
  { I960_INSN_BBS_REG, I960BASE_INSN_BBS_REG, I960BASE_SFMT_BBC_REG },
  { I960_INSN_BBS_LIT, I960BASE_INSN_BBS_LIT, I960BASE_SFMT_BBC_LIT },
  { I960_INSN_CMPI, I960BASE_INSN_CMPI, I960BASE_SFMT_CMPI },
  { I960_INSN_CMPI1, I960BASE_INSN_CMPI1, I960BASE_SFMT_CMPI1 },
  { I960_INSN_CMPI2, I960BASE_INSN_CMPI2, I960BASE_SFMT_CMPI2 },
  { I960_INSN_CMPI3, I960BASE_INSN_CMPI3, I960BASE_SFMT_CMPI3 },
  { I960_INSN_CMPO, I960BASE_INSN_CMPO, I960BASE_SFMT_CMPO },
  { I960_INSN_CMPO1, I960BASE_INSN_CMPO1, I960BASE_SFMT_CMPO1 },
  { I960_INSN_CMPO2, I960BASE_INSN_CMPO2, I960BASE_SFMT_CMPO2 },
  { I960_INSN_CMPO3, I960BASE_INSN_CMPO3, I960BASE_SFMT_CMPO3 },
  { I960_INSN_TESTNO_REG, I960BASE_INSN_TESTNO_REG, I960BASE_SFMT_TESTNO_REG },
  { I960_INSN_TESTG_REG, I960BASE_INSN_TESTG_REG, I960BASE_SFMT_TESTNO_REG },
  { I960_INSN_TESTE_REG, I960BASE_INSN_TESTE_REG, I960BASE_SFMT_TESTNO_REG },
  { I960_INSN_TESTGE_REG, I960BASE_INSN_TESTGE_REG, I960BASE_SFMT_TESTNO_REG },
  { I960_INSN_TESTL_REG, I960BASE_INSN_TESTL_REG, I960BASE_SFMT_TESTNO_REG },
  { I960_INSN_TESTNE_REG, I960BASE_INSN_TESTNE_REG, I960BASE_SFMT_TESTNO_REG },
  { I960_INSN_TESTLE_REG, I960BASE_INSN_TESTLE_REG, I960BASE_SFMT_TESTNO_REG },
  { I960_INSN_TESTO_REG, I960BASE_INSN_TESTO_REG, I960BASE_SFMT_TESTNO_REG },
  { I960_INSN_BNO, I960BASE_INSN_BNO, I960BASE_SFMT_BNO },
  { I960_INSN_BG, I960BASE_INSN_BG, I960BASE_SFMT_BNO },
  { I960_INSN_BE, I960BASE_INSN_BE, I960BASE_SFMT_BNO },
  { I960_INSN_BGE, I960BASE_INSN_BGE, I960BASE_SFMT_BNO },
  { I960_INSN_BL, I960BASE_INSN_BL, I960BASE_SFMT_BNO },
  { I960_INSN_BNE, I960BASE_INSN_BNE, I960BASE_SFMT_BNO },
  { I960_INSN_BLE, I960BASE_INSN_BLE, I960BASE_SFMT_BNO },
  { I960_INSN_BO, I960BASE_INSN_BO, I960BASE_SFMT_BNO },
  { I960_INSN_B, I960BASE_INSN_B, I960BASE_SFMT_B },
  { I960_INSN_BX_INDIRECT_OFFSET, I960BASE_INSN_BX_INDIRECT_OFFSET, I960BASE_SFMT_BX_INDIRECT_OFFSET },
  { I960_INSN_BX_INDIRECT, I960BASE_INSN_BX_INDIRECT, I960BASE_SFMT_BX_INDIRECT },
  { I960_INSN_BX_INDIRECT_INDEX, I960BASE_INSN_BX_INDIRECT_INDEX, I960BASE_SFMT_BX_INDIRECT_INDEX },
  { I960_INSN_BX_DISP, I960BASE_INSN_BX_DISP, I960BASE_SFMT_BX_DISP },
  { I960_INSN_BX_INDIRECT_DISP, I960BASE_INSN_BX_INDIRECT_DISP, I960BASE_SFMT_BX_INDIRECT_DISP },
  { I960_INSN_CALLX_DISP, I960BASE_INSN_CALLX_DISP, I960BASE_SFMT_CALLX_DISP },
  { I960_INSN_CALLX_INDIRECT, I960BASE_INSN_CALLX_INDIRECT, I960BASE_SFMT_CALLX_INDIRECT },
  { I960_INSN_CALLX_INDIRECT_OFFSET, I960BASE_INSN_CALLX_INDIRECT_OFFSET, I960BASE_SFMT_CALLX_INDIRECT_OFFSET },
  { I960_INSN_RET, I960BASE_INSN_RET, I960BASE_SFMT_RET },
  { I960_INSN_CALLS, I960BASE_INSN_CALLS, I960BASE_SFMT_CALLS },
  { I960_INSN_FMARK, I960BASE_INSN_FMARK, I960BASE_SFMT_FMARK },
  { I960_INSN_FLUSHREG, I960BASE_INSN_FLUSHREG, I960BASE_SFMT_FLUSHREG },
};

static const struct insn_sem i960base_insn_sem_invalid = {
  VIRTUAL_INSN_X_INVALID, I960BASE_INSN_X_INVALID, I960BASE_SFMT_EMPTY
};

/* Initialize an IDESC from the compile-time computable parts.  */

static INLINE void
init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
{
  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;

  id->num = t->index;
  id->sfmt = t->sfmt;
  if ((int) t->type <= 0)
    id->idata = & cgen_virtual_insn_table[- (int) t->type];
  else
    id->idata = & insn_table[t->type];
  id->attrs = CGEN_INSN_ATTRS (id->idata);
  /* Oh my god, a magic number.  */
  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;

#if WITH_PROFILE_MODEL_P
  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
  {
    SIM_DESC sd = CPU_STATE (cpu);
    SIM_ASSERT (t->index == id->timing->num);
  }
#endif

  /* Semantic pointers are initialized elsewhere.  */
}

/* Initialize the instruction descriptor table.  */

void
i960base_init_idesc_table (SIM_CPU *cpu)
{
  IDESC *id,*tabend;
  const struct insn_sem *t,*tend;
  int tabsize = I960BASE_INSN_MAX;
  IDESC *table = i960base_insn_data;

  memset (table, 0, tabsize * sizeof (IDESC));

  /* First set all entries to the `invalid insn'.  */
  t = & i960base_insn_sem_invalid;
  for (id = table, tabend = table + tabsize; id < tabend; ++id)
    init_idesc (cpu, id, t);

  /* Now fill in the values for the chosen cpu.  */
  for (t = i960base_insn_sem, tend = t + sizeof (i960base_insn_sem) / sizeof (*t);
       t != tend; ++t)
    {
      init_idesc (cpu, & table[t->index], t);
    }

  /* Link the IDESC table into the cpu.  */
  CPU_IDESC (cpu) = table;
}

/* Given an instruction, return a pointer to its IDESC entry.  */

const IDESC *
i960base_decode (SIM_CPU *current_cpu, IADDR pc,
              CGEN_INSN_INT base_insn,
              ARGBUF *abuf)
{
  /* Result of decoder.  */
  I960BASE_INSN_TYPE itype;

  {
    CGEN_INSN_INT insn = base_insn;

    {
      unsigned int val = (((insn >> 24) & (255 << 0)));
      switch (val)
      {
      case 8 : itype = I960BASE_INSN_B; goto extract_sfmt_b;
      case 10 : itype = I960BASE_INSN_RET; goto extract_sfmt_ret;
      case 16 : itype = I960BASE_INSN_BNO; goto extract_sfmt_bno;
      case 17 : itype = I960BASE_INSN_BG; goto extract_sfmt_bno;
      case 18 : itype = I960BASE_INSN_BE; goto extract_sfmt_bno;
      case 19 : itype = I960BASE_INSN_BGE; goto extract_sfmt_bno;
      case 20 : itype = I960BASE_INSN_BL; goto extract_sfmt_bno;
      case 21 : itype = I960BASE_INSN_BNE; goto extract_sfmt_bno;
      case 22 : itype = I960BASE_INSN_BLE; goto extract_sfmt_bno;
      case 23 : itype = I960BASE_INSN_BO; goto extract_sfmt_bno;
      case 32 : itype = I960BASE_INSN_TESTNO_REG; goto extract_sfmt_testno_reg;
      case 33 : itype = I960BASE_INSN_TESTG_REG; goto extract_sfmt_testno_reg;
      case 34 : itype = I960BASE_INSN_TESTE_REG; goto extract_sfmt_testno_reg;
      case 35 : itype = I960BASE_INSN_TESTGE_REG; goto extract_sfmt_testno_reg;
      case 36 : itype = I960BASE_INSN_TESTL_REG; goto extract_sfmt_testno_reg;
      case 37 : itype = I960BASE_INSN_TESTNE_REG; goto extract_sfmt_testno_reg;
      case 38 : itype = I960BASE_INSN_TESTLE_REG; goto extract_sfmt_testno_reg;
      case 39 : itype = I960BASE_INSN_TESTO_REG; goto extract_sfmt_testno_reg;
      case 48 :
        {
          unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
          switch (val)
          {
          case 0 : itype = I960BASE_INSN_BBC_REG; goto extract_sfmt_bbc_reg;
          case 4 : itype = I960BASE_INSN_BBC_LIT; goto extract_sfmt_bbc_lit;
          default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty;
          }
        }
      case 49 :
        {
          unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
          switch (val)
          {
          case 0 : itype = I960BASE_INSN_CMPOBG_REG; goto extract_sfmt_cmpobl_reg;
          case 4 : itype = I960BASE_INSN_CMPOBG_LIT; goto extract_sfmt_cmpobl_lit;
          default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty;
          }
        }
      case 50 :
        {
          unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
          switch (val)
          {
          case 0 : itype = I960BASE_INSN_CMPOBE_REG; goto extract_sfmt_cmpobe_reg;
          case 4 : itype = I960BASE_INSN_CMPOBE_LIT; goto extract_sfmt_cmpobe_lit;
          default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty;
          }
        }
      case 51 :
        {
          unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
          switch (val)
          {
          case 0 : itype = I960BASE_INSN_CMPOBGE_REG; goto extract_sfmt_cmpobl_reg;
          case 4 : itype = I960BASE_INSN_CMPOBGE_LIT; goto extract_sfmt_cmpobl_lit;
          default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty;
          }
        }
      case 52 :
        {
          unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
          switch (val)
          {
          case 0 : itype = I960BASE_INSN_CMPOBL_REG; goto extract_sfmt_cmpobl_reg;
          case 4 : itype = I960BASE_INSN_CMPOBL_LIT; goto extract_sfmt_cmpobl_lit;
          default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty;
          }
        }
      case 53 :
        {
          unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
          switch (val)
          {
          case 0 : itype = I960BASE_INSN_CMPOBNE_REG; goto extract_sfmt_cmpobe_reg;
          case 4 : itype = I960BASE_INSN_CMPOBNE_LIT; goto extract_sfmt_cmpobe_lit;
          default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty;
          }
        }
      case 54 :
        {
          unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
          switch (val)
          {
          case 0 : itype = I960BASE_INSN_CMPOBLE_REG; goto extract_sfmt_cmpobl_reg;