sem-switch.c

这个是LINUX下的GDB调度工具的源码

/* Simulator instruction semantics for i960base.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.

This file is part of the GNU Simulators.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifdef DEFINE_LABELS

  /* The labels have the case they have because the enum of insn types
     is all uppercase and in the non-stdc case the insn symbol is built
     into the enum name.  */

  static struct {
    int index;
    void *label;
  } labels[] = {
    { I960BASE_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
    { I960BASE_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
    { I960BASE_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
    { I960BASE_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
    { I960BASE_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
    { I960BASE_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
    { I960BASE_INSN_MULO, && case_sem_INSN_MULO },
    { I960BASE_INSN_MULO1, && case_sem_INSN_MULO1 },
    { I960BASE_INSN_MULO2, && case_sem_INSN_MULO2 },
    { I960BASE_INSN_MULO3, && case_sem_INSN_MULO3 },
    { I960BASE_INSN_REMO, && case_sem_INSN_REMO },
    { I960BASE_INSN_REMO1, && case_sem_INSN_REMO1 },
    { I960BASE_INSN_REMO2, && case_sem_INSN_REMO2 },
    { I960BASE_INSN_REMO3, && case_sem_INSN_REMO3 },
    { I960BASE_INSN_DIVO, && case_sem_INSN_DIVO },
    { I960BASE_INSN_DIVO1, && case_sem_INSN_DIVO1 },
    { I960BASE_INSN_DIVO2, && case_sem_INSN_DIVO2 },
    { I960BASE_INSN_DIVO3, && case_sem_INSN_DIVO3 },
    { I960BASE_INSN_REMI, && case_sem_INSN_REMI },
    { I960BASE_INSN_REMI1, && case_sem_INSN_REMI1 },
    { I960BASE_INSN_REMI2, && case_sem_INSN_REMI2 },
    { I960BASE_INSN_REMI3, && case_sem_INSN_REMI3 },
    { I960BASE_INSN_DIVI, && case_sem_INSN_DIVI },
    { I960BASE_INSN_DIVI1, && case_sem_INSN_DIVI1 },
    { I960BASE_INSN_DIVI2, && case_sem_INSN_DIVI2 },
    { I960BASE_INSN_DIVI3, && case_sem_INSN_DIVI3 },
    { I960BASE_INSN_ADDO, && case_sem_INSN_ADDO },
    { I960BASE_INSN_ADDO1, && case_sem_INSN_ADDO1 },
    { I960BASE_INSN_ADDO2, && case_sem_INSN_ADDO2 },
    { I960BASE_INSN_ADDO3, && case_sem_INSN_ADDO3 },
    { I960BASE_INSN_SUBO, && case_sem_INSN_SUBO },
    { I960BASE_INSN_SUBO1, && case_sem_INSN_SUBO1 },
    { I960BASE_INSN_SUBO2, && case_sem_INSN_SUBO2 },
    { I960BASE_INSN_SUBO3, && case_sem_INSN_SUBO3 },
    { I960BASE_INSN_NOTBIT, && case_sem_INSN_NOTBIT },
    { I960BASE_INSN_NOTBIT1, && case_sem_INSN_NOTBIT1 },
    { I960BASE_INSN_NOTBIT2, && case_sem_INSN_NOTBIT2 },
    { I960BASE_INSN_NOTBIT3, && case_sem_INSN_NOTBIT3 },
    { I960BASE_INSN_AND, && case_sem_INSN_AND },
    { I960BASE_INSN_AND1, && case_sem_INSN_AND1 },
    { I960BASE_INSN_AND2, && case_sem_INSN_AND2 },
    { I960BASE_INSN_AND3, && case_sem_INSN_AND3 },
    { I960BASE_INSN_ANDNOT, && case_sem_INSN_ANDNOT },
    { I960BASE_INSN_ANDNOT1, && case_sem_INSN_ANDNOT1 },
    { I960BASE_INSN_ANDNOT2, && case_sem_INSN_ANDNOT2 },
    { I960BASE_INSN_ANDNOT3, && case_sem_INSN_ANDNOT3 },
    { I960BASE_INSN_SETBIT, && case_sem_INSN_SETBIT },
    { I960BASE_INSN_SETBIT1, && case_sem_INSN_SETBIT1 },
    { I960BASE_INSN_SETBIT2, && case_sem_INSN_SETBIT2 },
    { I960BASE_INSN_SETBIT3, && case_sem_INSN_SETBIT3 },
    { I960BASE_INSN_NOTAND, && case_sem_INSN_NOTAND },
    { I960BASE_INSN_NOTAND1, && case_sem_INSN_NOTAND1 },
    { I960BASE_INSN_NOTAND2, && case_sem_INSN_NOTAND2 },
    { I960BASE_INSN_NOTAND3, && case_sem_INSN_NOTAND3 },
    { I960BASE_INSN_XOR, && case_sem_INSN_XOR },
    { I960BASE_INSN_XOR1, && case_sem_INSN_XOR1 },
    { I960BASE_INSN_XOR2, && case_sem_INSN_XOR2 },
    { I960BASE_INSN_XOR3, && case_sem_INSN_XOR3 },
    { I960BASE_INSN_OR, && case_sem_INSN_OR },
    { I960BASE_INSN_OR1, && case_sem_INSN_OR1 },
    { I960BASE_INSN_OR2, && case_sem_INSN_OR2 },
    { I960BASE_INSN_OR3, && case_sem_INSN_OR3 },
    { I960BASE_INSN_NOR, && case_sem_INSN_NOR },
    { I960BASE_INSN_NOR1, && case_sem_INSN_NOR1 },
    { I960BASE_INSN_NOR2, && case_sem_INSN_NOR2 },
    { I960BASE_INSN_NOR3, && case_sem_INSN_NOR3 },
    { I960BASE_INSN_XNOR, && case_sem_INSN_XNOR },
    { I960BASE_INSN_XNOR1, && case_sem_INSN_XNOR1 },
    { I960BASE_INSN_XNOR2, && case_sem_INSN_XNOR2 },
    { I960BASE_INSN_XNOR3, && case_sem_INSN_XNOR3 },
    { I960BASE_INSN_NOT, && case_sem_INSN_NOT },
    { I960BASE_INSN_NOT1, && case_sem_INSN_NOT1 },
    { I960BASE_INSN_NOT2, && case_sem_INSN_NOT2 },
    { I960BASE_INSN_NOT3, && case_sem_INSN_NOT3 },
    { I960BASE_INSN_ORNOT, && case_sem_INSN_ORNOT },
    { I960BASE_INSN_ORNOT1, && case_sem_INSN_ORNOT1 },
    { I960BASE_INSN_ORNOT2, && case_sem_INSN_ORNOT2 },
    { I960BASE_INSN_ORNOT3, && case_sem_INSN_ORNOT3 },
    { I960BASE_INSN_CLRBIT, && case_sem_INSN_CLRBIT },
    { I960BASE_INSN_CLRBIT1, && case_sem_INSN_CLRBIT1 },
    { I960BASE_INSN_CLRBIT2, && case_sem_INSN_CLRBIT2 },
    { I960BASE_INSN_CLRBIT3, && case_sem_INSN_CLRBIT3 },
    { I960BASE_INSN_SHLO, && case_sem_INSN_SHLO },
    { I960BASE_INSN_SHLO1, && case_sem_INSN_SHLO1 },
    { I960BASE_INSN_SHLO2, && case_sem_INSN_SHLO2 },
    { I960BASE_INSN_SHLO3, && case_sem_INSN_SHLO3 },
    { I960BASE_INSN_SHRO, && case_sem_INSN_SHRO },
    { I960BASE_INSN_SHRO1, && case_sem_INSN_SHRO1 },
    { I960BASE_INSN_SHRO2, && case_sem_INSN_SHRO2 },
    { I960BASE_INSN_SHRO3, && case_sem_INSN_SHRO3 },
    { I960BASE_INSN_SHLI, && case_sem_INSN_SHLI },
    { I960BASE_INSN_SHLI1, && case_sem_INSN_SHLI1 },
    { I960BASE_INSN_SHLI2, && case_sem_INSN_SHLI2 },
    { I960BASE_INSN_SHLI3, && case_sem_INSN_SHLI3 },
    { I960BASE_INSN_SHRI, && case_sem_INSN_SHRI },
    { I960BASE_INSN_SHRI1, && case_sem_INSN_SHRI1 },
    { I960BASE_INSN_SHRI2, && case_sem_INSN_SHRI2 },
    { I960BASE_INSN_SHRI3, && case_sem_INSN_SHRI3 },
    { I960BASE_INSN_EMUL, && case_sem_INSN_EMUL },
    { I960BASE_INSN_EMUL1, && case_sem_INSN_EMUL1 },
    { I960BASE_INSN_EMUL2, && case_sem_INSN_EMUL2 },
    { I960BASE_INSN_EMUL3, && case_sem_INSN_EMUL3 },
    { I960BASE_INSN_MOV, && case_sem_INSN_MOV },
    { I960BASE_INSN_MOV1, && case_sem_INSN_MOV1 },
    { I960BASE_INSN_MOVL, && case_sem_INSN_MOVL },
    { I960BASE_INSN_MOVL1, && case_sem_INSN_MOVL1 },
    { I960BASE_INSN_MOVT, && case_sem_INSN_MOVT },
    { I960BASE_INSN_MOVT1, && case_sem_INSN_MOVT1 },
    { I960BASE_INSN_MOVQ, && case_sem_INSN_MOVQ },
    { I960BASE_INSN_MOVQ1, && case_sem_INSN_MOVQ1 },
    { I960BASE_INSN_MODPC, && case_sem_INSN_MODPC },
    { I960BASE_INSN_MODAC, && case_sem_INSN_MODAC },
    { I960BASE_INSN_LDA_OFFSET, && case_sem_INSN_LDA_OFFSET },
    { I960BASE_INSN_LDA_INDIRECT_OFFSET, && case_sem_INSN_LDA_INDIRECT_OFFSET },
    { I960BASE_INSN_LDA_INDIRECT, && case_sem_INSN_LDA_INDIRECT },
    { I960BASE_INSN_LDA_INDIRECT_INDEX, && case_sem_INSN_LDA_INDIRECT_INDEX },
    { I960BASE_INSN_LDA_DISP, && case_sem_INSN_LDA_DISP },
    { I960BASE_INSN_LDA_INDIRECT_DISP, && case_sem_INSN_LDA_INDIRECT_DISP },
    { I960BASE_INSN_LDA_INDEX_DISP, && case_sem_INSN_LDA_INDEX_DISP },
    { I960BASE_INSN_LDA_INDIRECT_INDEX_DISP, && case_sem_INSN_LDA_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_LD_OFFSET, && case_sem_INSN_LD_OFFSET },
    { I960BASE_INSN_LD_INDIRECT_OFFSET, && case_sem_INSN_LD_INDIRECT_OFFSET },
    { I960BASE_INSN_LD_INDIRECT, && case_sem_INSN_LD_INDIRECT },
    { I960BASE_INSN_LD_INDIRECT_INDEX, && case_sem_INSN_LD_INDIRECT_INDEX },
    { I960BASE_INSN_LD_DISP, && case_sem_INSN_LD_DISP },
    { I960BASE_INSN_LD_INDIRECT_DISP, && case_sem_INSN_LD_INDIRECT_DISP },
    { I960BASE_INSN_LD_INDEX_DISP, && case_sem_INSN_LD_INDEX_DISP },
    { I960BASE_INSN_LD_INDIRECT_INDEX_DISP, && case_sem_INSN_LD_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_LDOB_OFFSET, && case_sem_INSN_LDOB_OFFSET },
    { I960BASE_INSN_LDOB_INDIRECT_OFFSET, && case_sem_INSN_LDOB_INDIRECT_OFFSET },
    { I960BASE_INSN_LDOB_INDIRECT, && case_sem_INSN_LDOB_INDIRECT },
    { I960BASE_INSN_LDOB_INDIRECT_INDEX, && case_sem_INSN_LDOB_INDIRECT_INDEX },
    { I960BASE_INSN_LDOB_DISP, && case_sem_INSN_LDOB_DISP },
    { I960BASE_INSN_LDOB_INDIRECT_DISP, && case_sem_INSN_LDOB_INDIRECT_DISP },
    { I960BASE_INSN_LDOB_INDEX_DISP, && case_sem_INSN_LDOB_INDEX_DISP },
    { I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP, && case_sem_INSN_LDOB_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_LDOS_OFFSET, && case_sem_INSN_LDOS_OFFSET },
    { I960BASE_INSN_LDOS_INDIRECT_OFFSET, && case_sem_INSN_LDOS_INDIRECT_OFFSET },
    { I960BASE_INSN_LDOS_INDIRECT, && case_sem_INSN_LDOS_INDIRECT },
    { I960BASE_INSN_LDOS_INDIRECT_INDEX, && case_sem_INSN_LDOS_INDIRECT_INDEX },
    { I960BASE_INSN_LDOS_DISP, && case_sem_INSN_LDOS_DISP },
    { I960BASE_INSN_LDOS_INDIRECT_DISP, && case_sem_INSN_LDOS_INDIRECT_DISP },
    { I960BASE_INSN_LDOS_INDEX_DISP, && case_sem_INSN_LDOS_INDEX_DISP },
    { I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP, && case_sem_INSN_LDOS_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_LDIB_OFFSET, && case_sem_INSN_LDIB_OFFSET },
    { I960BASE_INSN_LDIB_INDIRECT_OFFSET, && case_sem_INSN_LDIB_INDIRECT_OFFSET },
    { I960BASE_INSN_LDIB_INDIRECT, && case_sem_INSN_LDIB_INDIRECT },
    { I960BASE_INSN_LDIB_INDIRECT_INDEX, && case_sem_INSN_LDIB_INDIRECT_INDEX },
    { I960BASE_INSN_LDIB_DISP, && case_sem_INSN_LDIB_DISP },
    { I960BASE_INSN_LDIB_INDIRECT_DISP, && case_sem_INSN_LDIB_INDIRECT_DISP },
    { I960BASE_INSN_LDIB_INDEX_DISP, && case_sem_INSN_LDIB_INDEX_DISP },
    { I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP, && case_sem_INSN_LDIB_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_LDIS_OFFSET, && case_sem_INSN_LDIS_OFFSET },
    { I960BASE_INSN_LDIS_INDIRECT_OFFSET, && case_sem_INSN_LDIS_INDIRECT_OFFSET },
    { I960BASE_INSN_LDIS_INDIRECT, && case_sem_INSN_LDIS_INDIRECT },
    { I960BASE_INSN_LDIS_INDIRECT_INDEX, && case_sem_INSN_LDIS_INDIRECT_INDEX },
    { I960BASE_INSN_LDIS_DISP, && case_sem_INSN_LDIS_DISP },
    { I960BASE_INSN_LDIS_INDIRECT_DISP, && case_sem_INSN_LDIS_INDIRECT_DISP },
    { I960BASE_INSN_LDIS_INDEX_DISP, && case_sem_INSN_LDIS_INDEX_DISP },
    { I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP, && case_sem_INSN_LDIS_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_LDL_OFFSET, && case_sem_INSN_LDL_OFFSET },
    { I960BASE_INSN_LDL_INDIRECT_OFFSET, && case_sem_INSN_LDL_INDIRECT_OFFSET },
    { I960BASE_INSN_LDL_INDIRECT, && case_sem_INSN_LDL_INDIRECT },
    { I960BASE_INSN_LDL_INDIRECT_INDEX, && case_sem_INSN_LDL_INDIRECT_INDEX },
    { I960BASE_INSN_LDL_DISP, && case_sem_INSN_LDL_DISP },
    { I960BASE_INSN_LDL_INDIRECT_DISP, && case_sem_INSN_LDL_INDIRECT_DISP },
    { I960BASE_INSN_LDL_INDEX_DISP, && case_sem_INSN_LDL_INDEX_DISP },
    { I960BASE_INSN_LDL_INDIRECT_INDEX_DISP, && case_sem_INSN_LDL_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_LDT_OFFSET, && case_sem_INSN_LDT_OFFSET },
    { I960BASE_INSN_LDT_INDIRECT_OFFSET, && case_sem_INSN_LDT_INDIRECT_OFFSET },
    { I960BASE_INSN_LDT_INDIRECT, && case_sem_INSN_LDT_INDIRECT },
    { I960BASE_INSN_LDT_INDIRECT_INDEX, && case_sem_INSN_LDT_INDIRECT_INDEX },
    { I960BASE_INSN_LDT_DISP, && case_sem_INSN_LDT_DISP },
    { I960BASE_INSN_LDT_INDIRECT_DISP, && case_sem_INSN_LDT_INDIRECT_DISP },
    { I960BASE_INSN_LDT_INDEX_DISP, && case_sem_INSN_LDT_INDEX_DISP },
    { I960BASE_INSN_LDT_INDIRECT_INDEX_DISP, && case_sem_INSN_LDT_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_LDQ_OFFSET, && case_sem_INSN_LDQ_OFFSET },
    { I960BASE_INSN_LDQ_INDIRECT_OFFSET, && case_sem_INSN_LDQ_INDIRECT_OFFSET },
    { I960BASE_INSN_LDQ_INDIRECT, && case_sem_INSN_LDQ_INDIRECT },
    { I960BASE_INSN_LDQ_INDIRECT_INDEX, && case_sem_INSN_LDQ_INDIRECT_INDEX },
    { I960BASE_INSN_LDQ_DISP, && case_sem_INSN_LDQ_DISP },
    { I960BASE_INSN_LDQ_INDIRECT_DISP, && case_sem_INSN_LDQ_INDIRECT_DISP },
    { I960BASE_INSN_LDQ_INDEX_DISP, && case_sem_INSN_LDQ_INDEX_DISP },
    { I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP, && case_sem_INSN_LDQ_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_ST_OFFSET, && case_sem_INSN_ST_OFFSET },
    { I960BASE_INSN_ST_INDIRECT_OFFSET, && case_sem_INSN_ST_INDIRECT_OFFSET },
    { I960BASE_INSN_ST_INDIRECT, && case_sem_INSN_ST_INDIRECT },
    { I960BASE_INSN_ST_INDIRECT_INDEX, && case_sem_INSN_ST_INDIRECT_INDEX },
    { I960BASE_INSN_ST_DISP, && case_sem_INSN_ST_DISP },
    { I960BASE_INSN_ST_INDIRECT_DISP, && case_sem_INSN_ST_INDIRECT_DISP },
    { I960BASE_INSN_ST_INDEX_DISP, && case_sem_INSN_ST_INDEX_DISP },
    { I960BASE_INSN_ST_INDIRECT_INDEX_DISP, && case_sem_INSN_ST_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_STOB_OFFSET, && case_sem_INSN_STOB_OFFSET },
    { I960BASE_INSN_STOB_INDIRECT_OFFSET, && case_sem_INSN_STOB_INDIRECT_OFFSET },
    { I960BASE_INSN_STOB_INDIRECT, && case_sem_INSN_STOB_INDIRECT },
    { I960BASE_INSN_STOB_INDIRECT_INDEX, && case_sem_INSN_STOB_INDIRECT_INDEX },
    { I960BASE_INSN_STOB_DISP, && case_sem_INSN_STOB_DISP },
    { I960BASE_INSN_STOB_INDIRECT_DISP, && case_sem_INSN_STOB_INDIRECT_DISP },
    { I960BASE_INSN_STOB_INDEX_DISP, && case_sem_INSN_STOB_INDEX_DISP },
    { I960BASE_INSN_STOB_INDIRECT_INDEX_DISP, && case_sem_INSN_STOB_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_STOS_OFFSET, && case_sem_INSN_STOS_OFFSET },
    { I960BASE_INSN_STOS_INDIRECT_OFFSET, && case_sem_INSN_STOS_INDIRECT_OFFSET },
    { I960BASE_INSN_STOS_INDIRECT, && case_sem_INSN_STOS_INDIRECT },
    { I960BASE_INSN_STOS_INDIRECT_INDEX, && case_sem_INSN_STOS_INDIRECT_INDEX },
    { I960BASE_INSN_STOS_DISP, && case_sem_INSN_STOS_DISP },
    { I960BASE_INSN_STOS_INDIRECT_DISP, && case_sem_INSN_STOS_INDIRECT_DISP },
    { I960BASE_INSN_STOS_INDEX_DISP, && case_sem_INSN_STOS_INDEX_DISP },
    { I960BASE_INSN_STOS_INDIRECT_INDEX_DISP, && case_sem_INSN_STOS_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_STL_OFFSET, && case_sem_INSN_STL_OFFSET },
    { I960BASE_INSN_STL_INDIRECT_OFFSET, && case_sem_INSN_STL_INDIRECT_OFFSET },
    { I960BASE_INSN_STL_INDIRECT, && case_sem_INSN_STL_INDIRECT },
    { I960BASE_INSN_STL_INDIRECT_INDEX, && case_sem_INSN_STL_INDIRECT_INDEX },
    { I960BASE_INSN_STL_DISP, && case_sem_INSN_STL_DISP },
    { I960BASE_INSN_STL_INDIRECT_DISP, && case_sem_INSN_STL_INDIRECT_DISP },
    { I960BASE_INSN_STL_INDEX_DISP, && case_sem_INSN_STL_INDEX_DISP },
    { I960BASE_INSN_STL_INDIRECT_INDEX_DISP, && case_sem_INSN_STL_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_STT_OFFSET, && case_sem_INSN_STT_OFFSET },
    { I960BASE_INSN_STT_INDIRECT_OFFSET, && case_sem_INSN_STT_INDIRECT_OFFSET },
    { I960BASE_INSN_STT_INDIRECT, && case_sem_INSN_STT_INDIRECT },
    { I960BASE_INSN_STT_INDIRECT_INDEX, && case_sem_INSN_STT_INDIRECT_INDEX },
    { I960BASE_INSN_STT_DISP, && case_sem_INSN_STT_DISP },
    { I960BASE_INSN_STT_INDIRECT_DISP, && case_sem_INSN_STT_INDIRECT_DISP },
    { I960BASE_INSN_STT_INDEX_DISP, && case_sem_INSN_STT_INDEX_DISP },
    { I960BASE_INSN_STT_INDIRECT_INDEX_DISP, && case_sem_INSN_STT_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_STQ_OFFSET, && case_sem_INSN_STQ_OFFSET },
    { I960BASE_INSN_STQ_INDIRECT_OFFSET, && case_sem_INSN_STQ_INDIRECT_OFFSET },
    { I960BASE_INSN_STQ_INDIRECT, && case_sem_INSN_STQ_INDIRECT },
    { I960BASE_INSN_STQ_INDIRECT_INDEX, && case_sem_INSN_STQ_INDIRECT_INDEX },
    { I960BASE_INSN_STQ_DISP, && case_sem_INSN_STQ_DISP },
    { I960BASE_INSN_STQ_INDIRECT_DISP, && case_sem_INSN_STQ_INDIRECT_DISP },
    { I960BASE_INSN_STQ_INDEX_DISP, && case_sem_INSN_STQ_INDEX_DISP },
    { I960BASE_INSN_STQ_INDIRECT_INDEX_DISP, && case_sem_INSN_STQ_INDIRECT_INDEX_DISP },
    { I960BASE_INSN_CMPOBE_REG, && case_sem_INSN_CMPOBE_REG },
    { I960BASE_INSN_CMPOBE_LIT, && case_sem_INSN_CMPOBE_LIT },
    { I960BASE_INSN_CMPOBNE_REG, && case_sem_INSN_CMPOBNE_REG },
    { I960BASE_INSN_CMPOBNE_LIT, && case_sem_INSN_CMPOBNE_LIT },
    { I960BASE_INSN_CMPOBL_REG, && case_sem_INSN_CMPOBL_REG },
    { I960BASE_INSN_CMPOBL_LIT, && case_sem_INSN_CMPOBL_LIT },
    { I960BASE_INSN_CMPOBLE_REG, && case_sem_INSN_CMPOBLE_REG },
    { I960BASE_INSN_CMPOBLE_LIT, && case_sem_INSN_CMPOBLE_LIT },
    { I960BASE_INSN_CMPOBG_REG, && case_sem_INSN_CMPOBG_REG },
    { I960BASE_INSN_CMPOBG_LIT, && case_sem_INSN_CMPOBG_LIT },
    { I960BASE_INSN_CMPOBGE_REG, && case_sem_INSN_CMPOBGE_REG },
    { I960BASE_INSN_CMPOBGE_LIT, && case_sem_INSN_CMPOBGE_LIT },
    { I960BASE_INSN_CMPIBE_REG, && case_sem_INSN_CMPIBE_REG },
    { I960BASE_INSN_CMPIBE_LIT, && case_sem_INSN_CMPIBE_LIT },
    { I960BASE_INSN_CMPIBNE_REG, && case_sem_INSN_CMPIBNE_REG },
    { I960BASE_INSN_CMPIBNE_LIT, && case_sem_INSN_CMPIBNE_LIT },
    { I960BASE_INSN_CMPIBL_REG, && case_sem_INSN_CMPIBL_REG },
    { I960BASE_INSN_CMPIBL_LIT, && case_sem_INSN_CMPIBL_LIT },
    { I960BASE_INSN_CMPIBLE_REG, && case_sem_INSN_CMPIBLE_REG },
    { I960BASE_INSN_CMPIBLE_LIT, && case_sem_INSN_CMPIBLE_LIT },
    { I960BASE_INSN_CMPIBG_REG, && case_sem_INSN_CMPIBG_REG },
    { I960BASE_INSN_CMPIBG_LIT, && case_sem_INSN_CMPIBG_LIT },
    { I960BASE_INSN_CMPIBGE_REG, && case_sem_INSN_CMPIBGE_REG },
    { I960BASE_INSN_CMPIBGE_LIT, && case_sem_INSN_CMPIBGE_LIT },
    { I960BASE_INSN_BBC_REG, && case_sem_INSN_BBC_REG },
    { I960BASE_INSN_BBC_LIT, && case_sem_INSN_BBC_LIT },
    { I960BASE_INSN_BBS_REG, && case_sem_INSN_BBS_REG },
    { I960BASE_INSN_BBS_LIT, && case_sem_INSN_BBS_LIT },
    { I960BASE_INSN_CMPI, && case_sem_INSN_CMPI },
    { I960BASE_INSN_CMPI1, && case_sem_INSN_CMPI1 },
    { I960BASE_INSN_CMPI2, && case_sem_INSN_CMPI2 },
    { I960BASE_INSN_CMPI3, && case_sem_INSN_CMPI3 },
    { I960BASE_INSN_CMPO, && case_sem_INSN_CMPO },
    { I960BASE_INSN_CMPO1, && case_sem_INSN_CMPO1 },
    { I960BASE_INSN_CMPO2, && case_sem_INSN_CMPO2 },
    { I960BASE_INSN_CMPO3, && case_sem_INSN_CMPO3 },
    { I960BASE_INSN_TESTNO_REG, && case_sem_INSN_TESTNO_REG },
    { I960BASE_INSN_TESTG_REG, && case_sem_INSN_TESTG_REG },
    { I960BASE_INSN_TESTE_REG, && case_sem_INSN_TESTE_REG },
    { I960BASE_INSN_TESTGE_REG, && case_sem_INSN_TESTGE_REG },
    { I960BASE_INSN_TESTL_REG, && case_sem_INSN_TESTL_REG },
    { I960BASE_INSN_TESTNE_REG, && case_sem_INSN_TESTNE_REG },
    { I960BASE_INSN_TESTLE_REG, && case_sem_INSN_TESTLE_REG },
    { I960BASE_INSN_TESTO_REG, && case_sem_INSN_TESTO_REG },
    { I960BASE_INSN_BNO, && case_sem_INSN_BNO },
    { I960BASE_INSN_BG, && case_sem_INSN_BG },
    { I960BASE_INSN_BE, && case_sem_INSN_BE },
    { I960BASE_INSN_BGE, && case_sem_INSN_BGE },
    { I960BASE_INSN_BL, && case_sem_INSN_BL },
    { I960BASE_INSN_BNE, && case_sem_INSN_BNE },
    { I960BASE_INSN_BLE, && case_sem_INSN_BLE },
    { I960BASE_INSN_BO, && case_sem_INSN_BO },
    { I960BASE_INSN_B, && case_sem_INSN_B },
    { I960BASE_INSN_BX_INDIRECT_OFFSET, && case_sem_INSN_BX_INDIRECT_OFFSET },
    { I960BASE_INSN_BX_INDIRECT, && case_sem_INSN_BX_INDIRECT },
    { I960BASE_INSN_BX_INDIRECT_INDEX, && case_sem_INSN_BX_INDIRECT_INDEX },
    { I960BASE_INSN_BX_DISP, && case_sem_INSN_BX_DISP },
    { I960BASE_INSN_BX_INDIRECT_DISP, && case_sem_INSN_BX_INDIRECT_DISP },
    { I960BASE_INSN_CALLX_DISP, && case_sem_INSN_CALLX_DISP },
    { I960BASE_INSN_CALLX_INDIRECT, && case_sem_INSN_CALLX_INDIRECT },
    { I960BASE_INSN_CALLX_INDIRECT_OFFSET, && case_sem_INSN_CALLX_INDIRECT_OFFSET },
    { I960BASE_INSN_RET, && case_sem_INSN_RET },
    { I960BASE_INSN_CALLS, && case_sem_INSN_CALLS },
    { I960BASE_INSN_FMARK, && case_sem_INSN_FMARK },
    { I960BASE_INSN_FLUSHREG, && case_sem_INSN_FLUSHREG },
    { 0, 0 }
  };
  int i;

  for (i = 0; labels[i].label != 0; ++i)
    {
#if FAST_P
      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
#else
      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
#endif
    }

#undef DEFINE_LABELS
#endif /* DEFINE_LABELS */

#ifdef DEFINE_SWITCH

/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
   off frills like tracing and profiling.  */
/* FIXME: A better way would be to have TRACE_RESULT check for something
   that can cause it to be optimized out.  Another way would be to emit
   special handlers into the instruction "stream".  */

#if FAST_P
#undef TRACE_RESULT
#define TRACE_RESULT(cpu, abuf, name, type, val)
#endif

#undef GET_ATTR
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)

{

#if WITH_SCACHE_PBB

/* Branch to next handler without going around main loop.  */
#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)

#else /* ! WITH_SCACHE_PBB */

#define NEXT(vpc) BREAK (sem)
#ifdef __GNUC__
#if FAST_P
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
#else
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
#endif
#else
  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
#endif

#endif /* ! WITH_SCACHE_PBB */

    {

  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {
    /* Update the recorded pc in the cpu state struct.
       Only necessary for WITH_SCACHE case, but to avoid the
       conditional compilation ....  */
    SET_H_PC (pc);
    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
       using the default-insn-bitsize spec.  When executing insns in parallel
       we may want to queue the fault and continue execution.  */
    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_X_AFTER) : /* --after-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {
#if WITH_SCACHE_PBB_I960BASE
    i960base_pbb_after (current_cpu, sem_arg);
#endif
  }

#undef FLD
}
  NEXT (vpc);

  CASE (sem, INSN_X_BEFORE) : /* --before-- */
{
  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
  int UNUSED written = 0;
  IADDR UNUSED pc = abuf->addr;
  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {