i960-desc.c

这个是LINUX下的GDB调度工具的源码

    I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bbc $br_src1, $br_src2, $br_disp */
  {
    I960_INSN_BBC_REG, "bbc-reg", "bbc", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bbc $br_lit1, $br_src2, $br_disp */
  {
    I960_INSN_BBC_LIT, "bbc-lit", "bbc", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bbs $br_src1, $br_src2, $br_disp */
  {
    I960_INSN_BBS_REG, "bbs-reg", "bbs", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bbs $br_lit1, $br_src2, $br_disp */
  {
    I960_INSN_BBS_LIT, "bbs-lit", "bbs", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* cmpi $src1, $src2 */
  {
    I960_INSN_CMPI, "cmpi", "cmpi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmpi $lit1, $src2 */
  {
    I960_INSN_CMPI1, "cmpi1", "cmpi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmpi $src1, $lit2 */
  {
    I960_INSN_CMPI2, "cmpi2", "cmpi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmpi $lit1, $lit2 */
  {
    I960_INSN_CMPI3, "cmpi3", "cmpi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmpo $src1, $src2 */
  {
    I960_INSN_CMPO, "cmpo", "cmpo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmpo $lit1, $src2 */
  {
    I960_INSN_CMPO1, "cmpo1", "cmpo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmpo $src1, $lit2 */
  {
    I960_INSN_CMPO2, "cmpo2", "cmpo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmpo $lit1, $lit2 */
  {
    I960_INSN_CMPO3, "cmpo3", "cmpo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* testno $br_src1 */
  {
    I960_INSN_TESTNO_REG, "testno-reg", "testno", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* testg $br_src1 */
  {
    I960_INSN_TESTG_REG, "testg-reg", "testg", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* teste $br_src1 */
  {
    I960_INSN_TESTE_REG, "teste-reg", "teste", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* testge $br_src1 */
  {
    I960_INSN_TESTGE_REG, "testge-reg", "testge", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* testl $br_src1 */
  {
    I960_INSN_TESTL_REG, "testl-reg", "testl", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* testne $br_src1 */
  {
    I960_INSN_TESTNE_REG, "testne-reg", "testne", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* testle $br_src1 */
  {
    I960_INSN_TESTLE_REG, "testle-reg", "testle", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* testo $br_src1 */
  {
    I960_INSN_TESTO_REG, "testo-reg", "testo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* bno $ctrl_disp */
  {
    I960_INSN_BNO, "bno", "bno", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bg $ctrl_disp */
  {
    I960_INSN_BG, "bg", "bg", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* be $ctrl_disp */
  {
    I960_INSN_BE, "be", "be", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bge $ctrl_disp */
  {
    I960_INSN_BGE, "bge", "bge", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bl $ctrl_disp */
  {
    I960_INSN_BL, "bl", "bl", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bne $ctrl_disp */
  {
    I960_INSN_BNE, "bne", "bne", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* ble $ctrl_disp */
  {
    I960_INSN_BLE, "ble", "ble", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* bo $ctrl_disp */
  {
    I960_INSN_BO, "bo", "bo", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
  },
/* b $ctrl_disp */
  {
    I960_INSN_B, "b", "b", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* bx $offset($abase) */
  {
    I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* bx ($abase) */
  {
    I960_INSN_BX_INDIRECT, "bx-indirect", "bx", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* bx ($abase)[$index*S$scale] */
  {
    I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* bx $optdisp */
  {
    I960_INSN_BX_DISP, "bx-disp", "bx", 64,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* bx $optdisp($abase) */
  {
    I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx", 64,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* callx $optdisp */
  {
    I960_INSN_CALLX_DISP, "callx-disp", "callx", 64,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* callx ($abase) */
  {
    I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* callx $offset($abase) */
  {
    I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* ret */
  {
    I960_INSN_RET, "ret", "ret", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* calls $src1 */
  {
    I960_INSN_CALLS, "calls", "calls", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* fmark */
  {
    I960_INSN_FMARK, "fmark", "fmark", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
  },
/* flushreg */
  {
    I960_INSN_FLUSHREG, "flushreg", "flushreg", 32,
    { 0, { (1<<MACH_BASE) } }
  },
};

#undef A
#undef MNEM
#undef OP

/* Initialize anything needed to be done once, before any cpu_open call.  */

static void
init_tables ()
{
}

/* Subroutine of i960_cgen_cpu_open to look up a mach via its bfd name.  */

static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
     const CGEN_MACH *table;
     const char *name;
{
  while (table->name)
    {
      if (strcmp (name, table->bfd_name) == 0)
	return table;
      ++table;
    }
  abort ();
}

/* Subroutine of i960_cgen_cpu_open to build the hardware table.  */

static void
build_hw_table (cd)
     CGEN_CPU_TABLE *cd;
{
  int i;
  int machs = cd->machs;
  const CGEN_HW_ENTRY *init = & i960_cgen_hw_table[0];
  /* MAX_HW is only an upper bound on the number of selected entries.
     However each entry is indexed by it's enum so there can be holes in
     the table.  */
  const CGEN_HW_ENTRY **selected =
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));

  cd->hw_table.init_entries = init;
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
  /* ??? For now we just use machs to determine which ones we want.  */
  for (i = 0; init[i].name != NULL; ++i)
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
	& machs)
      selected[init[i].type] = &init[i];
  cd->hw_table.entries = selected;
  cd->hw_table.num_entries = MAX_HW;
}

/* Subroutine of i960_cgen_cpu_open to build the hardware table.  */

static void
build_ifield_table (cd)
     CGEN_CPU_TABLE *cd;
{
  cd->ifld_table = & i960_cgen_ifld_table[0];
}

/* Subroutine of i960_cgen_cpu_open to build the hardware table.  */

static void
build_operand_table (cd)
     CGEN_CPU_TABLE *cd;
{
  int i;
  int machs = cd->machs;
  const CGEN_OPERAND *init = & i960_cgen_operand_table[0];
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
     However each entry is indexed by it's enum so there can be holes in
     the table.  */
  const CGEN_OPERAND **selected =
    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));

  cd->operand_table.init_entries = init;
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
  /* ??? For now we just use mach to determine which ones we want.  */
  for (i = 0; init[i].name != NULL; ++i)
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
	& machs)
      selected[init[i].type] = &init[i];
  cd->operand_table.entries = selected;
  cd->operand_table.num_entries = MAX_OPERANDS;
}

/* Subroutine of i960_cgen_cpu_open to build the hardware table.
   ??? This could leave out insns not supported by the specified mach/isa,
   but that would cause errors like "foo only supported by bar" to become
   "unknown insn", so for now we include all insns and require the app to
   do the checking later.
   ??? On the other hand, parsing of such insns may require their hardware or
   operand elements to be in the table [which they mightn't be].  */

static void
build_insn_table (cd)
     CGEN_CPU_TABLE *cd;
{
  int i;
  const CGEN_IBASE *ib = & i960_cgen_insn_table[0];
  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));

  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
  for (i = 0; i < MAX_INSNS; ++i)
    insns[i].base = &ib[i];
  cd->insn_table.init_entries = insns;
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
  cd->insn_table.num_init_entries = MAX_INSNS;
}

/* Subroutine of i960_cgen_cpu_open to rebuild the tables.  */

static void
i960_cgen_rebuild_tables (cd)
     CGEN_CPU_TABLE *cd;
{
  int i,n_isas,n_machs;
  unsigned int isas = cd->isas;
  unsigned int machs = cd->machs;

  cd->int_insn_p = CGEN_INT_INSN_P;

  /* Data derived from the isa spec.  */
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
  cd->default_insn_bitsize = UNSET;
  cd->base_insn_bitsize = UNSET;
  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
  cd->max_insn_bitsize = 0;
  for (i = 0; i < MAX_ISAS; ++i)
    if (((1 << i) & isas) != 0)
      {
	const CGEN_ISA *isa = & i960_cgen_isa_table[i];

	/* Default insn sizes of all selected isas must be equal or we set
	   the result to 0, meaning "unknown".  */
	if (cd->default_insn_bitsize == UNSET)
	  cd->default_insn_bitsize = isa->default_insn_bitsize;
	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
	  ; /* this is ok */
	else
	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;

	/* Base insn sizes of all selected isas must be equal or we set
	   the result to 0, meaning "unknown".  */
	if (cd->base_insn_bitsize == UNSET)
	  cd->base_insn_bitsize = isa->base_insn_bitsize;
	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
	  ; /* this is ok */
	else
	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;

	/* Set min,max insn sizes.  */
	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
	  cd->min_insn_bitsize = isa->min_insn_bitsize;
	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
	  cd->max_insn_bitsize = isa->max_insn_bitsize;

	++n_isas;
      }

  /* Data derived from the mach spec.  */
  for (i = 0; i < MAX_MACHS; ++i)
    if (((1 << i) & machs) != 0)
      {
	const CGEN_MACH *mach = & i960_cgen_mach_table[i];

	++n_machs;
      }

  /* Determine which hw elements are used by MACH.  */
  build_hw_table (cd);

  /* Build the ifield table.  */
  build_ifield_table (cd);

  /* Determine which operands are used by MACH/ISA.  */
  build_operand_table (cd);

  /* Build the instruction table.  */
  build_insn_table (cd);
}

/* Initialize a cpu table and return a descriptor.
   It's much like opening a file, and must be the first function called.
   The arguments are a set of (type/value) pairs, terminated with
   CGEN_CPU_OPEN_END.

   Currently supported values:
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
   CGEN_CPU_OPEN_END:     terminates arguments

   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
   precluded.

   ??? We only support ISO C stdargs here, not K&R.
   Laziness, plus experiment to see if anything requires K&R - eventually
   K&R will no longer be supported - e.g. GDB is currently trying this.  */

CGEN_CPU_DESC
i960_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
{
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
  static int init_p;
  unsigned int isas = 0;  /* 0 = "unspecified" */
  unsigned int machs = 0; /* 0 = "unspecified" */
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
  va_list ap;

  if (! init_p)
    {
      init_tables ();
      init_p = 1;
    }

  memset (cd, 0, sizeof (*cd));

  va_start (ap, arg_type);
  while (arg_type != CGEN_CPU_OPEN_END)
    {
      switch (arg_type)
	{
	case CGEN_CPU_OPEN_ISAS :
	  isas = va_arg (ap, unsigned int);
	  break;
	case CGEN_CPU_OPEN_MACHS :
	  machs = va_arg (ap, unsigned int);
	  break;
	case CGEN_CPU_OPEN_BFDMACH :
	  {
	    const char *name = va_arg (ap, const char *);
	    const CGEN_MACH *mach =
	      lookup_mach_via_bfd_name (i960_cgen_mach_table, name);

	    machs |= mach->num << 1;
	    break;
	  }
	case CGEN_CPU_OPEN_ENDIAN :
	  endian = va_arg (ap, enum cgen_endian);
	  break;
	default :
	  fprintf (stderr, "i960_cgen_cpu_open: unsupported argument `%d'\n",
		   arg_type);
	  abort (); /* ??? return NULL? */
	}
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
    }
  va_end (ap);

  /* mach unspecified means "all" */
  if (machs == 0)
    machs = (1 << MAX_MACHS) - 1;
  /* base mach is always selected */
  machs |= 1;
  /* isa unspecified means "all" */
  if (isas == 0)
    isas = (1 << MAX_ISAS) - 1;
  if (endian == CGEN_ENDIAN_UNKNOWN)
    {
      /* ??? If target has only one, could have a default.  */
      fprintf (stderr, "i960_cgen_cpu_open: no endianness specified\n");
      abort ();
    }

  cd->isas = isas;
  cd->machs = machs;
  cd->endian = endian;
  /* FIXME: for the sparc case we can determine insn-endianness statically.
     The worry here is where both data and insn endian can be independently
     chosen, in which case this function will need another argument.
     Actually, will want to allow for more arguments in the future anyway.  */
  cd->insn_endian = endian;

  /* Table (re)builder.  */
  cd->rebuild_tables = i960_cgen_rebuild_tables;
  i960_cgen_rebuild_tables (cd);

  return (CGEN_CPU_DESC) cd;
}

/* Cover fn to i960_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
   MACH_NAME is the bfd name of the mach.  */

CGEN_CPU_DESC
i960_cgen_cpu_open_1 (mach_name, endian)
     const char *mach_name;
     enum cgen_endian endian;
{
  return i960_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
			       CGEN_CPU_OPEN_ENDIAN, endian,
			       CGEN_CPU_OPEN_END);
}

/* Close a cpu table.
   ??? This can live in a machine independent file, but there's currently
   no place to put this file (there's no libcgen).  libopcodes is the wrong
   place as some simulator ports use this but they don't use libopcodes.  */

void
i960_cgen_cpu_close (cd)
     CGEN_CPU_DESC cd;
{
  if (cd->insn_table.init_entries)
    free ((CGEN_INSN *) cd->insn_table.init_entries);
  if (cd->hw_table.entries)
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
  free (cd);
}