i960-desc.c

这个是LINUX下的GDB调度工具的源码

/* CPU data for i960.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright (C) 1996, 1997, 1998, 1999, 2001 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#include "sysdep.h"
#include <ctype.h>
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "i960-desc.h"
#include "i960-opc.h"
#include "opintl.h"

/* Attributes.  */

static const CGEN_ATTR_ENTRY bool_attr[] =
{
  { "#f", 0 },
  { "#t", 1 },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY MACH_attr[] =
{
  { "base", MACH_BASE },
  { "i960_ka_sa", MACH_I960_KA_SA },
  { "i960_ca", MACH_I960_CA },
  { "max", MACH_MAX },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY ISA_attr[] =
{
  { "i960", ISA_I960 },
  { "max", ISA_MAX },
  { 0, 0 }
};

const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] =
{
  { "MACH", & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
{
  { "MACH", & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  { "PC", &bool_attr[0], &bool_attr[0] },
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
{
  { "MACH", & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
{
  { "MACH", & MACH_attr[0] },
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
  { "PBB", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

/* Instruction set variants.  */

static const CGEN_ISA i960_cgen_isa_table[] = {
  { "i960", 32, 32, 32, 64,  },
  { 0 }
};

/* Machine variants.  */

static const CGEN_MACH i960_cgen_mach_table[] = {
  { "i960:ka_sa", "i960:ka_sa", MACH_I960_KA_SA },
  { "i960:ca", "i960:ca", MACH_I960_CA },
  { 0 }
};

static CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
{
  { "fp", 31 },
  { "sp", 1 },
  { "r0", 0 },
  { "r1", 1 },
  { "r2", 2 },
  { "r3", 3 },
  { "r4", 4 },
  { "r5", 5 },
  { "r6", 6 },
  { "r7", 7 },
  { "r8", 8 },
  { "r9", 9 },
  { "r10", 10 },
  { "r11", 11 },
  { "r12", 12 },
  { "r13", 13 },
  { "r14", 14 },
  { "r15", 15 },
  { "g0", 16 },
  { "g1", 17 },
  { "g2", 18 },
  { "g3", 19 },
  { "g4", 20 },
  { "g5", 21 },
  { "g6", 22 },
  { "g7", 23 },
  { "g8", 24 },
  { "g9", 25 },
  { "g10", 26 },
  { "g11", 27 },
  { "g12", 28 },
  { "g13", 29 },
  { "g14", 30 },
  { "g15", 31 }
};

CGEN_KEYWORD i960_cgen_opval_h_gr =
{
  & i960_cgen_opval_h_gr_entries[0],
  34
};

static CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] =
{
  { "cc", 0 }
};

CGEN_KEYWORD i960_cgen_opval_h_cc =
{
  & i960_cgen_opval_h_cc_entries[0],
  1
};



/* The hardware table.  */

#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_HW_##a)
#else
#define A(a) (1 << CGEN_HW_/**/a)
#endif

const CGEN_HW_ENTRY i960_cgen_hw_table[] =
{
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
  { 0 }
};

#undef A

/* The instruction field table.  */

#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_IFLD_##a)
#else
#define A(a) (1 << CGEN_IFLD_/**/a)
#endif

const CGEN_IFLD i960_cgen_ifld_table[] =
{
  { I960_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_M3, "f-m3", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_M2, "f-m2", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_M1, "f-m1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_INDEX, "f-index", 0, 32, 27, 5, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { 0, { (1<<MACH_BASE) } }  },
  { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { 0, { (1<<MACH_BASE) } }  },
  { 0 }
};

#undef A

/* The operand table.  */

#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_OPERAND_##a)
#else
#define A(a) (1 << CGEN_OPERAND_/**/a)
#endif
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define OPERAND(op) I960_OPERAND_##op
#else
#define OPERAND(op) I960_OPERAND_/**/op
#endif

const CGEN_OPERAND i960_cgen_operand_table[] =
{
/* pc: program counter */
  { "pc", I960_OPERAND_PC, HW_H_PC, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* src1: source register 1 */
  { "src1", I960_OPERAND_SRC1, HW_H_GR, 27, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* src2: source register 2 */
  { "src2", I960_OPERAND_SRC2, HW_H_GR, 13, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* dst: source/dest register */
  { "dst", I960_OPERAND_DST, HW_H_GR, 8, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* lit1: literal 1 */
  { "lit1", I960_OPERAND_LIT1, HW_H_UINT, 27, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* lit2: literal 2 */
  { "lit2", I960_OPERAND_LIT2, HW_H_UINT, 13, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* st_src: store src */
  { "st_src", I960_OPERAND_ST_SRC, HW_H_GR, 8, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* abase: abase */
  { "abase", I960_OPERAND_ABASE, HW_H_GR, 13, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* offset: offset */
  { "offset", I960_OPERAND_OFFSET, HW_H_UINT, 20, 12,
    { 0, { (1<<MACH_BASE) } }  },
/* scale: scale */
  { "scale", I960_OPERAND_SCALE, HW_H_UINT, 22, 3,
    { 0, { (1<<MACH_BASE) } }  },
/* index: index */
  { "index", I960_OPERAND_INDEX, HW_H_GR, 27, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* optdisp: optional displacement */
  { "optdisp", I960_OPERAND_OPTDISP, HW_H_UINT, 0, 32,
    { 0, { (1<<MACH_BASE) } }  },
/* br_src1: branch src1 */
  { "br_src1", I960_OPERAND_BR_SRC1, HW_H_GR, 8, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* br_src2: branch src2 */
  { "br_src2", I960_OPERAND_BR_SRC2, HW_H_GR, 13, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* br_disp: branch displacement */
  { "br_disp", I960_OPERAND_BR_DISP, HW_H_IADDR, 19, 11,
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
/* br_lit1: branch literal 1 */
  { "br_lit1", I960_OPERAND_BR_LIT1, HW_H_UINT, 8, 5,
    { 0, { (1<<MACH_BASE) } }  },
/* ctrl_disp: ctrl branch disp */
  { "ctrl_disp", I960_OPERAND_CTRL_DISP, HW_H_IADDR, 8, 22,
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { 0 }
};

#undef A

#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_INSN_##a)
#else
#define A(a) (1 << CGEN_INSN_/**/a)
#endif

/* The instruction table.  */

static const CGEN_IBASE i960_cgen_insn_table[MAX_INSNS] =
{
  /* Special null first entry.
     A `num' value of zero is thus invalid.
     Also, the special `invalid' insn resides here.  */
  { 0, 0, 0 },
/* mulo $src1, $src2, $dst */
  {
    I960_INSN_MULO, "mulo", "mulo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* mulo $lit1, $src2, $dst */
  {
    I960_INSN_MULO1, "mulo1", "mulo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* mulo $src1, $lit2, $dst */
  {
    I960_INSN_MULO2, "mulo2", "mulo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* mulo $lit1, $lit2, $dst */
  {
    I960_INSN_MULO3, "mulo3", "mulo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* remo $src1, $src2, $dst */
  {
    I960_INSN_REMO, "remo", "remo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* remo $lit1, $src2, $dst */
  {
    I960_INSN_REMO1, "remo1", "remo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* remo $src1, $lit2, $dst */
  {
    I960_INSN_REMO2, "remo2", "remo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* remo $lit1, $lit2, $dst */
  {
    I960_INSN_REMO3, "remo3", "remo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* divo $src1, $src2, $dst */
  {
    I960_INSN_DIVO, "divo", "divo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* divo $lit1, $src2, $dst */
  {
    I960_INSN_DIVO1, "divo1", "divo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* divo $src1, $lit2, $dst */
  {
    I960_INSN_DIVO2, "divo2", "divo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* divo $lit1, $lit2, $dst */
  {
    I960_INSN_DIVO3, "divo3", "divo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* remi $src1, $src2, $dst */
  {
    I960_INSN_REMI, "remi", "remi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* remi $lit1, $src2, $dst */
  {
    I960_INSN_REMI1, "remi1", "remi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* remi $src1, $lit2, $dst */
  {
    I960_INSN_REMI2, "remi2", "remi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* remi $lit1, $lit2, $dst */
  {
    I960_INSN_REMI3, "remi3", "remi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* divi $src1, $src2, $dst */
  {
    I960_INSN_DIVI, "divi", "divi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* divi $lit1, $src2, $dst */
  {
    I960_INSN_DIVI1, "divi1", "divi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* divi $src1, $lit2, $dst */
  {
    I960_INSN_DIVI2, "divi2", "divi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* divi $lit1, $lit2, $dst */
  {
    I960_INSN_DIVI3, "divi3", "divi", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* addo $src1, $src2, $dst */
  {
    I960_INSN_ADDO, "addo", "addo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* addo $lit1, $src2, $dst */
  {
    I960_INSN_ADDO1, "addo1", "addo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* addo $src1, $lit2, $dst */
  {
    I960_INSN_ADDO2, "addo2", "addo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* addo $lit1, $lit2, $dst */
  {
    I960_INSN_ADDO3, "addo3", "addo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* subo $src1, $src2, $dst */
  {
    I960_INSN_SUBO, "subo", "subo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* subo $lit1, $src2, $dst */
  {
    I960_INSN_SUBO1, "subo1", "subo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* subo $src1, $lit2, $dst */
  {
    I960_INSN_SUBO2, "subo2", "subo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* subo $lit1, $lit2, $dst */
  {
    I960_INSN_SUBO3, "subo3", "subo", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* notbit $src1, $src2, $dst */
  {
    I960_INSN_NOTBIT, "notbit", "notbit", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* notbit $lit1, $src2, $dst */
  {
    I960_INSN_NOTBIT1, "notbit1", "notbit", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* notbit $src1, $lit2, $dst */
  {
    I960_INSN_NOTBIT2, "notbit2", "notbit", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* notbit $lit1, $lit2, $dst */
  {
    I960_INSN_NOTBIT3, "notbit3", "notbit", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* and $src1, $src2, $dst */
  {
    I960_INSN_AND, "and", "and", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* and $lit1, $src2, $dst */
  {
    I960_INSN_AND1, "and1", "and", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* and $src1, $lit2, $dst */
  {
    I960_INSN_AND2, "and2", "and", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* and $lit1, $lit2, $dst */
  {
    I960_INSN_AND3, "and3", "and", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* andnot $src1, $src2, $dst */
  {
    I960_INSN_ANDNOT, "andnot", "andnot", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* andnot $lit1, $src2, $dst */
  {
    I960_INSN_ANDNOT1, "andnot1", "andnot", 32,
    { 0, { (1<<MACH_BASE) } }
  },
/* andnot $src1, $lit2, $dst */
  {
    I960_INSN_ANDNOT2, "andnot2", "andnot", 32,