simops.c

这个是LINUX下的GDB调度工具的源码

  value <<= 1;
  value |= (PSW & PSW_CF ? 0x1 : 0);
  value &= 0xffff;
  State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0 (insn)] |= value;
  z = (value == 0);
  n = (value & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0));
}

/* btst imm8, dn */
void OP_F50400 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int z;

  temp = State.regs[REG_D0 + REG0_8 (insn)];
  temp &= (insn & 0xff);
  z = (temp == 0);
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= (z ? PSW_ZF : 0);
}

/* btst imm16, dn */
void OP_F7040000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int z, n, c;

  temp = State.regs[REG_D0 + REG0_16 (insn)];
  c = temp & 0x1;
  temp &= (insn & 0xffff);
  n = (temp & 0x8000) != 0;
  z = (temp == 0);
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= (z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0);
}

/* bset dm, (an) */
void OP_F020 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int z;

  temp = load_byte (State.regs[REG_A0 + REG1 (insn)]);
  z = (temp & State.regs[REG_D0 + REG0 (insn)]) == 0;
  temp |= State.regs[REG_D0 + REG0 (insn)];
  store_byte (State.regs[REG_A0 + REG1 (insn)], temp);
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= (z ? PSW_ZF : 0);
}

/* bclr dm, (an) */
void OP_F030 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int z;

  temp = load_byte (State.regs[REG_A0 + REG1 (insn)]);
  z = (temp & State.regs[REG_D0 + REG0 (insn)]) == 0;
  temp = temp & ~State.regs[REG_D0 + REG0 (insn)];
  store_byte (State.regs[REG_A0 + REG1 (insn)], temp);
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= (z ? PSW_ZF : 0);
}

/* beqx label:8 */
void OP_F5E800 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_ZX)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bnex label:8 */
void OP_F5E900 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_ZX))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bgtx label:8 */
void OP_F5E100 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!((PSW & PSW_ZX)
        || (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0))))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bgex label:8 */
void OP_F5E200 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0)))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* blex label:8 */
void OP_F5E300 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if ((PSW & PSW_ZX)
       || (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0)))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bltx label:8 */
void OP_F5E000 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (((PSW & PSW_NX) != 0) ^ ((PSW & PSW_VX) != 0))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bhix label:8 */
void OP_F5E500 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(((PSW & PSW_CX) != 0) || (PSW & PSW_ZX) != 0))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bccx label:8 */
void OP_F5E600 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_CX))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* blsx label:8 */
void OP_F5E700 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (((PSW & PSW_CX) != 0) || (PSW & PSW_ZX) != 0)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bcsx label:8 */
void OP_F5E400 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_CX)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bvcx label:8 */
void OP_F5EC00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_VX))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bvsx label:8 */
void OP_F5ED00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_VX)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bncx label:8 */
void OP_F5EE00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_NX))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bnsx label:8 */
void OP_F5EF00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_NX)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* beq label:8 */
void OP_E800 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_ZF)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bne label:8 */
void OP_E900 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_ZF))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bgt label:8 */
void OP_E100 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!((PSW & PSW_ZF)
        || (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0))))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bge label:8 */
void OP_E200 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!(((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0)))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* ble label:8 */
void OP_E300 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if ((PSW & PSW_ZF)
       || (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0)))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* blt label:8 */
void OP_E000 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (((PSW & PSW_NF) != 0) ^ ((PSW & PSW_VF) != 0))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bhi label:8 */
void OP_E500 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!(((PSW & PSW_CF) != 0) || (PSW & PSW_ZF) != 0))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bcc label:8 */
void OP_E600 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_CF))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bls label:8 */
void OP_E700 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (((PSW & PSW_CF) != 0) || (PSW & PSW_ZF) != 0)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bcs label:8 */
void OP_E400 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_CF)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bvc label:8 */
void OP_F5FC00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_VF))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bvs label:8 */
void OP_F5FD00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_VF)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bnc label:8 */
void OP_F5FE00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_NF))
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bns label:8 */
void OP_F5FF00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_NF)
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* bra label:8 */
void OP_EA00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
    State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT8 (insn & 0xff));
}

/* jmp (an) */
void OP_F000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_PC] = TRUNC (State.regs[REG_A0 + REG1 (insn)] - 2);
}

/* jmp label:16 */
void OP_FC0000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT16 (insn & 0xffff));
}

/* jmp label:24 */
void OP_F4E00000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_PC]
    = TRUNC (State.regs[REG_PC] + (((insn & 0xffff) << 8) + extension));
}

/* jsr (an) */
void OP_F001 (insn, extension)
     unsigned long insn, extension;
{
  unsigned int next_pc, sp;

  sp = State.regs[REG_SP];
  sp -= 4;
  State.regs[REG_SP] = sp;
  next_pc = State.regs[REG_PC] + 2;
  State.mem[sp] = next_pc & 0xff;
  State.mem[sp+1] = (next_pc & 0xff00) >> 8;
  State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
  State.regs[REG_PC] = TRUNC (State.regs[REG_A0 + REG1 (insn)] - 2);
}

/* jsr label:16 */
void OP_FD0000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned int next_pc, sp;

  sp = State.regs[REG_SP];
  sp -= 4;
  State.regs[REG_SP] = sp;
  next_pc = State.regs[REG_PC] + 3;
  State.mem[sp] = next_pc & 0xff;
  State.mem[sp+1] = (next_pc & 0xff00) >> 8;
  State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
  State.regs[REG_PC] = TRUNC (State.regs[REG_PC] + SEXT16 (insn & 0xffff));
}

/* jsr label:24 */
void OP_F4E10000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned int next_pc, sp;

  sp = State.regs[REG_SP];
  sp -= 4;
  State.regs[REG_SP] = sp;
  next_pc = State.regs[REG_PC] + 5;
  State.mem[sp] = next_pc & 0xff;
  State.mem[sp+1] = (next_pc & 0xff00) >> 8;
  State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
  State.regs[REG_PC]
    = TRUNC (State.regs[REG_PC] + (((insn & 0xffff) << 8) + extension));
}

/* rts */
void OP_FE (insn, extension)
     unsigned long insn, extension;
{
  unsigned int sp;

  sp = State.regs[REG_SP];
  State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
	      | (State.mem[sp+2] << 16));
  State.regs[REG_PC] -= 1;
  State.regs[REG_SP] += 4;
}

/* rti */
void OP_EB (insn, extension)
     unsigned long insn, extension;
{
  PSW = load_half (State.regs[REG_A0 +