simops.c

这个是LINUX下的GDB调度工具的源码

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
}

/* cmp an, dm */
void OP_F2E0 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
}

/* cmp an, am */
void OP_F260 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
}

/* cmp imm16, dn */
void OP_F7480000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
  imm = TRUNC (SEXT16 (insn & 0xffff));
  value = TRUNC (reg1 - imm);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
}

/* cmp imm24, dn */
void OP_F4780000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
  imm = TRUNC (((insn & 0xffff) << 8) + extension);
  value = TRUNC (reg1 - imm);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
}

/* cmp imm16, an */
void OP_EC0000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
  imm = TRUNC (insn & 0xffff);
  value = TRUNC (reg1 - imm);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
}

/* cmp imm24, an */
void OP_F47C0000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
  imm = TRUNC (((insn & 0xffff) << 8) + extension);
  value = TRUNC (reg1 - imm);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
}

/* and dn, dm */
void OP_F300 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = State.regs[REG_D0 + REG0 (insn)] & State.regs[REG_D0 + REG1 (insn)];
  temp &= 0xffff;
  State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* and imm8, dn */
void OP_F50000 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = State.regs[REG_D0 + REG0_8 (insn)] & (insn & 0xff);
  temp &= 0xffff;
  State.regs[REG_D0 + REG0_8 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0_8 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0_8 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* and imm16, dn */
void OP_F7000000 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = State.regs[REG_D0 + REG0_16 (insn)] & (insn & 0xffff);
  temp &= 0xffff;
  State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0_16 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* and imm16, psw */
void OP_F7100000 (insn, extension)
     unsigned long insn, extension;
{
  PSW &= (insn & 0xffff);
}

/* or dn, dm */
void OP_F310 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = State.regs[REG_D0 + REG0 (insn)] | State.regs[REG_D0 + REG1 (insn)];
  temp &= 0xffff;
  State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* or imm8, dn */
void OP_F50800 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = State.regs[REG_D0 + REG0_8 (insn)] | (insn & 0xff);
  temp &= 0xffff;
  State.regs[REG_D0 + REG0_8 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0_8 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0_8 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* or imm16, dn */
void OP_F7400000 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = State.regs[REG_D0 + REG0_16 (insn)] | (insn & 0xffff);
  temp &= 0xffff;
  State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0_16 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* or imm16, psw */
void OP_F7140000 (insn, extension)
     unsigned long insn, extension;
{
  PSW |= (insn & 0xffff);
}

/* xor dn, dm */
void OP_F320 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = State.regs[REG_D0 + REG0 (insn)] ^ State.regs[REG_D0 + REG1 (insn)];
  temp &= 0xffff;
  State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* xor imm16, dn */
void OP_F74C0000 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = State.regs[REG_D0 + REG0_16 (insn)] ^ (insn & 0xffff);
  temp &= 0xffff;
  State.regs[REG_D0 + REG0_16 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0_16 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0_16 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* not dn */
void OP_F3E4 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;
  unsigned long temp;

  temp = ~State.regs[REG_D0 + REG0 (insn)];
  temp &= 0xffff;
  State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* asr dn */
void OP_F338 (insn, extension)
     unsigned long insn, extension;
{
  long temp;
  int z, n, c, high;

  temp = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
  c = temp & 1;
  high = temp & 0x8000;
  temp >>= 1;
  temp |= high;
  temp &= 0xffff;
  State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0));
}

/* lsr dn */
void OP_F33C (insn, extension)
     unsigned long insn, extension;
{
  int z, n, c;
  long temp;

  temp = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
  c = temp & 1;
  temp >>= 1;
  temp &= 0xffff;
  State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0 (insn)] |= temp;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0));
}

/* ror dn */
void OP_F334 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long value;
  int c,n,z;

  value = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
  c = (value & 0x1);

  value >>= 1;
  value |= (PSW & PSW_CF ? 0x8000 : 0);
  value &= 0xffff;
  State.regs[REG_D0 + REG0 (insn)] &= ~0xffff;
  State.regs[REG_D0 + REG0 (insn)] |= value;
  z = (value == 0);
  n = (value & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0) | (c ? PSW_CF : 0));
}

/* rol dn */
void OP_F330 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long value;
  int c,n,z;

  value = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
  c = (value & 0x8000) ? 1 : 0;