simops.c

这个是LINUX下的GDB调度工具的源码

  value = TRUNC (reg1 + reg2 + ((PSW & PSW_CF) != 0));
  State.regs[REG_D0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (reg2 & 0xffff));
  cx = (value < reg1) || (value < reg2);
  v = ((reg2 & 0x8000) == (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* addnf imm8, an */
void OP_F50C00 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long reg1, imm, value;

  reg1 = State.regs[REG_A0 + REG0_8 (insn)];
  imm = SEXT8 (insn & 0xff);
  value = reg1 + imm;
  State.regs[REG_A0 + REG0_8 (insn)] = TRUNC (value);
}

/* sub dn, dm */
void OP_A0 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1);
  State.regs[REG_D0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* sub dm, an */
void OP_F210 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1);
  State.regs[REG_A0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* sub an, dm */
void OP_F2D0 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1);
  State.regs[REG_D0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* sub an, am */
void OP_F250 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1);
  State.regs[REG_A0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* sub imm16, dn */
void OP_F71C0000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
  imm = TRUNC (SEXT16 (insn & 0xffff));
  value = TRUNC (reg1 - imm);
  State.regs[REG_D0 + REG0_16 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* sub imm24, dn */
void OP_F4680000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
  imm = TRUNC (((insn & 0xffff) << 8) + extension);
  value = TRUNC (reg1 - imm);
  State.regs[REG_D0 + REG0_16 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* sub imm16, an */
void OP_F70C0000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
  imm = TRUNC (SEXT16 (insn & 0xffff));
  value = TRUNC (reg1 - imm);
  State.regs[REG_A0 + REG0_16 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* sub imm24, an */
void OP_F46C0000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
  imm = TRUNC (((insn & 0xffff) << 8) + extension);
  value = TRUNC (reg1 - imm);
  State.regs[REG_A0 + REG0_16 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* subc dm, dn */
void OP_F290 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1 - ((PSW & PSW_CF) != 0));
  State.regs[REG_D0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* mul dn, dm */
void OP_F340 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int n, z;

  temp = (SEXT16 (State.regs[REG_D0 + REG0 (insn)] & 0xffff)
          *  SEXT16 ((State.regs[REG_D0 + REG1 (insn)] & 0xffff)));
  State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffff;
  State.regs[REG_MDR] = temp >> 16;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* mulu dn, dm */
void OP_F350 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int n, z;

  temp = ((State.regs[REG_D0 + REG0 (insn)] & 0xffff)
          *  (State.regs[REG_D0 + REG1 (insn)] & 0xffff));
  State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffff;
  State.regs[REG_MDR] = temp >> 16;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}


/* divu dm, dn */
void OP_F360 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int n, z;

  temp = State.regs[REG_MDR];
  temp &= 0xffff;
  temp <<= 16;
  temp |= (State.regs[REG_D0 + REG0 (insn)] & 0xffff);
  State.regs[REG_MDR] = (temp
			  % (unsigned long)(State.regs[REG_D0 + REG1 (insn)] & 0xffff));
  temp /= (unsigned long)(State.regs[REG_D0 + REG1 (insn)] & 0xffff);
  State.regs[REG_D0 + REG0 (insn)] = temp & 0xffff;
  z = (State.regs[REG_D0 + REG0 (insn)] & 0xffff) == 0;
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x8000) != 0;
  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0));
}

/* cmp imm8, dn */
void OP_D800 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG0_8 (insn)]);
  imm = TRUNC (SEXT8 (insn & 0xff));
  value = TRUNC (reg1 - imm);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) < (imm & 0xffff));
  cx = (reg1 < imm);
  v = ((reg1 & 0x8000) != (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) != (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* cmp dn, dm */
void OP_F390 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF);
  PSW |= ((z ? PSW_ZF : 0) | ( n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0));
}

/* cmp dm, an */
void OP_F220 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
  value = TRUNC (reg2 - reg1);

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((reg1 & 0xffff) > (reg2 & 0xffff));
  cx = (reg1 > reg2);
  v = ((reg2 & 0x8000) != (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) != (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));