simops.c

这个是LINUX下的GDB调度工具的源码

     unsigned long insn, extension;
{
  store_byte ((State.regs[REG_A0 + REG1_16 (insn)]
	      + SEXT24 (((insn & 0xffff) << 8) + extension)),
	      State.regs[REG_D0 + REG0_16 (insn)]);
}

/* movb dm, (di,an) */
void OP_F0C0 (insn, extension)
     unsigned long insn, extension;
{
  store_byte ((State.regs[REG_A0 + REG1 (insn)]
	      + State.regs[REG_D0 + REG0_4 (insn)]),
	      State.regs[REG_D0 + REG0 (insn)]);
}

/* movb dn, (abs16) */
void OP_C40000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte ((insn & 0xffff), State.regs[REG_D0 + REG0_16 (insn)]);
}

/* movb dn, (abs24) */
void OP_F4440000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte (SEXT24 (((insn & 0xffff) << 8) + extension),
	     State.regs[REG_D0 + REG0_16 (insn)]);
}

/* movbu (an), dm */
void OP_30 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)]
    = load_byte (State.regs[REG_A0 + REG1 (insn)]);
}

/* movbu (d8,an), dm */
void OP_F53000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_8 (insn)]
    = load_byte ((State.regs[REG_A0 + REG1_8 (insn)] + SEXT8 (insn & 0xff)));
}

/* movbu (d16,an), dm */
void OP_F7500000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_byte ((State.regs[REG_A0 + REG1_16 (insn)]
		  + SEXT16 (insn & 0xffff)));
}

/* movbu (d24,am), dn */
void OP_F4900000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_byte ((State.regs[REG_A0 + REG1_16 (insn)]
		  + SEXT24 (((insn & 0xffff) << 8) + extension)));
}

/* movbu (di,an), dm */
void OP_F080 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)]
    = load_byte ((State.regs[REG_A0 + REG1 (insn)]
		  + State.regs[REG_D0 + REG0_4 (insn)]));
}

/* movbu (abs16), dn */
void OP_CC0000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff));
}

/* movbu (abs24), dn */
void OP_F4C80000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_byte ((((insn & 0xffff) << 8) + extension));
}

/* ext dn */
void OP_F3C1 (insn, extension)
     unsigned long insn, extension;
{
  if (State.regs[REG_D0 + REG1 (insn)] & 0x8000)
    State.regs[REG_MDR] = 0xffff;
  else
    State.regs[REG_MDR] = 0;
}

/* extx dn */
void OP_B0 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
}

/* extxu dn */
void OP_B4 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG0 (insn)] & 0xffff;
}

/* extxb dn */
void OP_B8 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
}

/* extxbu dn */
void OP_BC (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG0 (insn)] & 0xff;
}

/* add dn,dm */
void OP_90 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
  value = TRUNC (reg1 + reg2);
  State.regs[REG_D0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (reg2 & 0xffff));
  cx = (value < reg1) || (value < reg2);
  v = ((reg2 & 0x8000) == (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add dm, an */
void OP_F200 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
  value = TRUNC (reg1 + reg2);
  State.regs[REG_A0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (reg2 & 0xffff));
  cx = (value < reg1) || (value < reg2);
  v = ((reg2 & 0x8000) == (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add an, dm */
void OP_F2C0 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);
  value = TRUNC (reg1 + reg2);
  State.regs[REG_D0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (reg2 & 0xffff));
  cx = (value < reg1) || (value < reg2);
  v = ((reg2 & 0x8000) == (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add an,am */
void OP_F240 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_A0 + REG0 (insn)]);
  value = TRUNC (reg1 + reg2);
  State.regs[REG_A0 + REG0 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (reg2 & 0xffff));
  cx = (value < reg1) || (value < reg2);
  v = ((reg2 & 0x8000) == (reg1 & 0x8000)
       && (reg2 & 0x8000) != (value & 0x8000));
  vx = ((reg2 & 0x800000) == (reg1 & 0x800000)
        && (reg2 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add imm8, dn */
void OP_D400 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG0_8 (insn)]);
  imm = TRUNC (SEXT8 (insn & 0xff));
  value = TRUNC (reg1 + imm);
  State.regs[REG_D0 + REG0_8 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (imm & 0xffff));
  cx = (value < reg1) || (value < imm);
  v = ((reg1 & 0x8000) == (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) == (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add imm16, dn */
void OP_F7180000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
  imm = TRUNC (SEXT16 (insn & 0xffff));
  value = TRUNC (reg1 + imm);
  State.regs[REG_D0 + REG0_16 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (imm & 0xffff));
  cx = (value < reg1) || (value < imm);
  v = ((reg1 & 0x8000) == (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) == (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add imm24,dn */
void OP_F4600000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG0_16 (insn)]);
  imm = TRUNC (((insn & 0xffff) << 8) + extension);
  value = TRUNC (reg1 + imm);
  State.regs[REG_D0 + REG0_16 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (imm & 0xffff));
  cx = (value < reg1) || (value < imm);
  v = ((reg1 & 0x8000) == (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) == (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add imm8, an */
void OP_D000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG0_8 (insn)]);
  imm = TRUNC (SEXT8 (insn & 0xff));
  value = TRUNC (reg1 + imm);
  State.regs[REG_A0 + REG0_8 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (imm & 0xffff));
  cx = (value < reg1) || (value < imm);
  v = ((reg1 & 0x8000) == (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) == (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add imm16, an */
void OP_F7080000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
  imm = TRUNC (SEXT16 (insn & 0xffff));
  value = TRUNC (reg1 + imm);
  State.regs[REG_A0 + REG0_16 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff))
       || ((value & 0xffff) < (imm & 0xffff));
  cx = (value < reg1) || (value < imm);
  v = ((reg1 & 0x8000) == (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) == (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* add imm24, an */
void OP_F4640000 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, imm, value;

  reg1 = TRUNC (State.regs[REG_A0 + REG0_16 (insn)]);
  imm = TRUNC (((insn & 0xffff) << 8) + extension);
  value = TRUNC (reg1 + imm);
  State.regs[REG_A0 + REG0_16 (insn)] = value;

  z = ((value & 0xffff) == 0);
  zx = (value == 0);
  n = (value & 0x8000);
  nx = (value & 0x800000);
  c = ((value & 0xffff) < (reg1 & 0xffff)) || ((value & 0xffff) < (imm & 0xffff));
  cx = (value < reg1) || (value < imm);
  v = ((reg1 & 0x8000) == (imm & 0x8000)
       && (reg1 & 0x8000) != (value & 0x8000));
  vx = ((reg1 & 0x800000) == (imm & 0x800000)
        && (reg1 & 0x800000) != (value & 0x800000));

  PSW &= ~(PSW_ZF | PSW_NF | PSW_CF | PSW_VF
	   | PSW_ZX | PSW_NX | PSW_CX | PSW_VX);
  PSW |= ((z ? PSW_ZF : 0) | (n ? PSW_NF : 0)
	  | (c ? PSW_CF : 0) | (v ? PSW_VF : 0)
	  | (zx ? PSW_ZX : 0) | (nx ? PSW_NX : 0)
	  | (cx ? PSW_CX : 0) | (vx ? PSW_VX : 0));
}

/* addc dm,dn */
void OP_F280 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v, zx, cx, nx, vx;
  unsigned long reg1, reg2, value;

  reg1 = TRUNC (State.regs[REG_D0 + REG1 (insn)]);
  reg2 = TRUNC (State.regs[REG_D0 + REG0 (insn)]);