dv-m68hc11.c

这个是LINUX下的GDB调度工具的源码

  { M6811_EEON,  "EEON  ", "Enable On-chip EEprom" },
  { 0,  0, 0 }
};

io_reg_desc hprio_desc[] = {
  { M6811_RBOOT, "RBOOT ", "Read Bootstrap ROM" },
  { M6811_SMOD,  "SMOD  ", "Special Mode" },
  { M6811_MDA,   "MDA   ", "Mode Select A" },
  { M6811_IRV,   "IRV   ", "Internal Read Visibility" },
  { 0,  0, 0 }
};

io_reg_desc option_desc[] = {
  { M6811_ADPU,  "ADPU  ", "A/D Powerup" },
  { M6811_CSEL,  "CSEL  ", "A/D/EE Charge pump clock source select" },
  { M6811_IRQE,  "IRQE  ", "IRQ Edge/Level sensitive" },
  { M6811_DLY,   "DLY   ", "Stop exit turn on delay" },
  { M6811_CME,   "CME   ", "Clock Monitor Enable" },
  { M6811_CR1,   "CR1   ", "COP timer rate select (CR1)" },
  { M6811_CR0,   "CR0   ", "COP timer rate select (CR0)" },
  { 0,  0, 0 }
};

static void
m68hc11_info (struct hw *me)
{
  SIM_DESC sd;
  uint16 base = 0;
  sim_cpu *cpu;
  struct m68hc11sio *controller;
  uint8 val;
  
  sd = hw_system (me);
  cpu = STATE_CPU (sd, 0);
  controller = hw_data (me);

  base = cpu_get_io_base (cpu);
  sim_io_printf (sd, "M68HC11:\n");

  val = cpu->ios[M6811_HPRIO];
  print_io_byte (sd, "HPRIO ", hprio_desc, val, base + M6811_HPRIO);
  switch (cpu->cpu_mode)
    {
    case M6811_MDA | M6811_SMOD:
      sim_io_printf (sd, "[test]\n");
      break;
    case M6811_SMOD:
      sim_io_printf (sd, "[bootstrap]\n");
      break;
    case M6811_MDA:
      sim_io_printf (sd, "[extended]\n");
      break;
    default:
      sim_io_printf (sd, "[single]\n");
      break;
    }

  val = cpu->ios[M6811_CONFIG];
  print_io_byte (sd, "CONFIG", config_desc, val, base + M6811_CONFIG);
  sim_io_printf (sd, "\n");

  val = cpu->ios[M6811_OPTION];
  print_io_byte (sd, "OPTION", option_desc, val, base + M6811_OPTION);
  sim_io_printf (sd, "\n");

  val = cpu->ios[M6811_INIT];
  print_io_byte (sd, "INIT  ", 0, val, base + M6811_INIT);
  sim_io_printf (sd, "Ram = 0x%04x IO = 0x%04x\n",
		 (((uint16) (val & 0xF0)) << 8),
		 (((uint16) (val & 0x0F)) << 12));


  cpu_info (sd, cpu);
  interrupts_info (sd, &cpu->cpu_interrupts);
}

static int
m68hc11_ioctl (struct hw *me,
	       hw_ioctl_request request,
	       va_list ap)
{
  m68hc11_info (me);
  return 0;
}

/* Setup an oscillator on an input port.

   TON represents the time in seconds that the input port should be set to 1.
   TOFF is the time in seconds for the input port to be set to 0.

   The oscillator frequency is therefore 1 / (ton + toff).

   REPEAT indicates the number of 1 <-> 0 transitions until the oscillator
   stops.  */
int
m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
                           double ton, double toff, signed64 repeat)
{
  sim_cpu *cpu;
  struct input_osc *osc;
  double f;

  cpu = STATE_CPU (sd, 0);

  /* Find oscillator that corresponds to the input port.  */
  osc = find_oscillator (hw_data (cpu->hw_cpu), port);
  if (osc == 0)
    return -1;

  /* Compute the ON time in cpu cycles.  */
  f = (double) (cpu->cpu_frequency) * ton;
  osc->on_time = (signed64) (f / 4.0);
  if (osc->on_time < 1)
    osc->on_time = 1;

  /* Compute the OFF time in cpu cycles.  */
  f = (double) (cpu->cpu_frequency) * toff;
  osc->off_time = (signed64) (f / 4.0);
  if (osc->off_time < 1)
    osc->off_time = 1;

  osc->repeat = repeat;
  if (osc->event)
    hw_event_queue_deschedule (cpu->hw_cpu, osc->event);

  osc->event = hw_event_queue_schedule (cpu->hw_cpu,
                                        osc->value ? osc->on_time
                                        : osc->off_time,
                                        oscillator_handler, osc);
  return 0;
}

/* Clear the oscillator.  */
int
m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port)
{
  sim_cpu *cpu;
  struct input_osc *osc;

  cpu = STATE_CPU (sd, 0);
  osc = find_oscillator (hw_data (cpu->hw_cpu), port);
  if (osc == 0)
    return -1;

  if (osc->event)
    hw_event_queue_deschedule (cpu->hw_cpu, osc->event);
  osc->event = 0;
  osc->repeat = 0;
  return 0;
}

static int
get_frequency (const char *s, double *f)
{
  char *p;
  
  *f = strtod (s, &p);
  if (s == p)
    return -1;

  if (*p)
    {
      if (strcasecmp (p, "khz") == 0)
        *f = *f * 1000.0;
      else if (strcasecmp (p, "mhz") == 0)
        *f = *f  * 1000000.0;
      else if (strcasecmp (p, "hz") != 0)
        return -1;
    }
  return 0;
}

static SIM_RC
m68hc11_option_handler (SIM_DESC sd, sim_cpu *cpu,
                        int opt, char *arg, int is_command)
{
  struct m68hc11cpu *controller;
  double f;
  char *p;
  int i;
  int title_printed = 0;
  
  if (cpu == 0)
    cpu = STATE_CPU (sd, 0);

  controller = hw_data (cpu->hw_cpu);
  switch (opt)
    {
    case OPTION_OSC_SET:
      p = strchr (arg, ',');
      if (p)
        *p++ = 0;

      if (p == 0)
        sim_io_eprintf (sd, "No frequency specified\n");
      else if (get_frequency (p, &f) < 0 || f < 1.0e-8)
        sim_io_eprintf (sd, "Invalid frequency: '%s'\n", p);
      else if (m68hc11cpu_set_oscillator (sd, arg,
                                          1.0 / (f * 2.0),
                                          1.0 / (f * 2.0), LONG_MAX))
        sim_io_eprintf (sd, "Invalid input port: '%s'\n", arg);
      break;

    case OPTION_OSC_CLEAR:
      if (m68hc11cpu_clear_oscillator (sd, arg) != 0)
        sim_io_eprintf (sd, "Invalid input port: '%s'\n", arg);
      break;

    case OPTION_OSC_INFO:
      for (i = 0; i < controller->last_oscillator; i++)
        {
          signed64 t;
          struct input_osc *osc;

          osc = &controller->oscillators[i];
          if (osc->event)
            {
              double f;
              int cur_value;
              int next_value;
              char freq[32];

              if (title_printed == 0)
                {
                  title_printed = 1;
                  sim_io_printf (sd, " PORT  Frequency   Current"
                                 "    Next    Transition time\n");
                }

              f = (double) (osc->on_time + osc->off_time);
              f = (double) (cpu->cpu_frequency / 4) / f;
              t = hw_event_remain_time (cpu->hw_cpu, osc->event);

              if (f > 10000.0)
                sprintf (freq, "%6.2f", f / 1000.0);
              else
                sprintf (freq, "%6.2f", f);
              cur_value = osc->value ? 1 : 0;
              next_value = osc->value ? 0 : 1;
              if (f > 10000.0)
                sim_io_printf (sd, " %4.4s  %8.8s khz"
                               "      %d       %d    %35.35s\n",
                               osc->name, freq,
                               cur_value, next_value,
                               cycle_to_string (cpu, t,
                                                PRINT_TIME | PRINT_CYCLE));
              else
                sim_io_printf (sd, " %4.4s  %8.8s hz "
                               "      %d       %d    %35.35s\n",
                               osc->name, freq,
                               cur_value, next_value,
                               cycle_to_string (cpu, t,
                                                PRINT_TIME | PRINT_CYCLE));
            }
        }
      break;      
    }

  return SIM_RC_OK;
}

/* generic read/write */

static unsigned
m68hc11cpu_io_read_buffer (struct hw *me,
			   void *dest,
			   int space,
			   unsigned_word base,
			   unsigned nr_bytes)
{
  SIM_DESC sd;
  struct m68hc11cpu *controller = hw_data (me);
  sim_cpu *cpu;
  unsigned byte = 0;
  int result;
  
  HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));

  sd  = hw_system (me);
  cpu = STATE_CPU (sd, 0);

  if (base >= cpu->bank_start && base < cpu->bank_end)
    {
      address_word virt_addr = phys_to_virt (cpu, base);
      if (virt_addr != base)
        return sim_core_read_buffer (sd, cpu, space, dest,
                                     virt_addr, nr_bytes);
    }

  /* Handle reads for the sub-devices.  */
  base -= controller->attach_address;
  result = sim_core_read_buffer (sd, cpu,
				 io_map, dest, base, nr_bytes);
  if (result > 0)
    return result;
  
  while (nr_bytes)
    {
      if (base >= controller->attach_size)
	break;

      memcpy (dest, &cpu->ios[base], 1);
      dest = (char*) dest + 1;
      base++;
      byte++;
      nr_bytes--;
    }
  return byte;
}     

void
m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
                     unsigned addr, uint8 val)
{
  uint8 mask;
  uint8 delta;
  int check_interrupts = 0;
  int i;
  
  switch (addr)
    {
    case M6811_PORTA:
      if (cpu->ios[M6811_PACTL] & M6811_DDRA7)
        mask = 3;
      else
        mask = 0x83;

      val = val & mask;
      val |= cpu->ios[M6811_PORTA] & ~mask;
      delta = val ^ cpu->ios[M6811_PORTA];
      cpu->ios[M6811_PORTA] = val;
      if (delta & 0x80)
        {
          /* Pulse accumulator is enabled.  */
          if ((cpu->ios[M6811_PACTL] & M6811_PAEN)
              && !(cpu->ios[M6811_PACTL] & M6811_PAMOD))
            {
              int inc;

              /* Increment event counter according to rising/falling edge.  */
              if (cpu->ios[M6811_PACTL] & M6811_PEDGE)
                inc = (val & 0x80) ? 1 : 0;
              else
                inc = (val & 0x80) ? 0 : 1;

              cpu->ios[M6811_PACNT] += inc;

              /* Event counter overflowed.  */
              if (inc && cpu->ios[M6811_PACNT] == 0)
                {
                  cpu->ios[M6811_TFLG2] |= M6811_PAOVI;
                  check_interrupts = 1;
                }
            }
        }

      /* Scan IC3, IC2 and IC1.  Bit number is 3 - i.  */
      for (i = 0; i < 3; i++)
        {
          uint8 mask = (1 << i);
          
          if (delta & mask)
            {
              uint8 edge;
              int captured;

              edge = cpu->ios[M6811_TCTL2];
              edge = (edge >> (2 * i)) & 0x3;
              switch (edge)
                {
                case 0:
                  captured = 0;
                  break;
                case 1:
                  captured = (val & mask) != 0;
                  break;
                case 2:
                  captured = (val & mask) == 0;
                  break;
                default:
                  captured = 1;
                  break;
                }
              if (captured)
                {
                  cpu->ios[M6811_TFLG1] |= (1 << i);
                  hw_port_event (me, CAPTURE, M6811_TIC1 + 3 - i);
                  check_interrupts = 1;
                }
            }
        }
      break;

    case M6811_PORTC:
      mask = cpu->ios[M6811_DDRC];
      val = val & mask;
      val |= cpu->ios[M6811_PORTC] & ~mask;
      cpu->ios[M6811_PORTC] = val;
      break;

    case M6811_PORTD:
      mask = cpu->ios[M6811_DDRD];
      val = val & mask;
      val |= cpu->ios[M6811_PORTD] & ~mask;
      cpu->ios[M6811_PORTD] = val;
      break;

    default:
      break;
    }

  if (check_interrupts)
    interrupts_update_pending (&cpu->cpu_interrupts);
}

static void
m68hc11cpu_io_write (struct hw *me, sim_cpu *cpu,
                     unsigned_word addr, uint8 val)
{
  switch (addr)
    {
    case M6811_PORTA:
      hw_port_event (me, PORT_A, val);
      break;

    case M6811_PIOC:
      break;

    case M6811_PORTC:
      hw_port_event (me, PORT_C, val);
      break;

    case M6811_PORTB:
      hw_port_event (me, PORT_B, val);
      break;

    case M6811_PORTCL:
      break;

    case M6811_DDRC:
      break;

    case M6811_PORTD:
      hw_port_event (me, PORT_D, val);
      break;

    case M6811_DDRD:
      break;

    case M6811_TMSK2:
      
      break;
      
      /* Change the RAM and I/O mapping.  */
    case M6811_INIT:
      {
	uint8 old_bank = cpu->ios[M6811_INIT];
	
	cpu->ios[M6811_INIT] = val;

	/* Update IO mapping.  Detach from the old address
	   and attach to the new one.  */
	if ((old_bank & 0x0F) != (val & 0x0F))
	  {
            struct m68hc11cpu *controller = hw_data (me);

            hw_detach_address (hw_parent (me), M6811_IO_LEVEL,
                               controller->attach_space,
                               controller->attach_address,
                               controller->attach_size,
                               me);
            controller->attach_address = (val & 0x0F0) << 12;
            hw_attach_address (hw_parent (me), M6811_IO_LEVEL,
                               controller->attach_space,
                               controller->attach_address,
                               controller->attach_size,
                               me);
	  }
	if ((old_bank & 0xF0) != (val & 0xF0))
	  {
	    ;
	  }
	return;
      }

    /* Writing the config is similar to programing the eeprom.
       The config register value is the last byte of the EEPROM.
       This last byte is not mapped in memory (that's why we have
       to add '1' to 'end_addr').  */
    case M6811_CONFIG:
      {
        return;
      }
      

      /* COP reset.  */
    case M6811_COPRST:
      if (val == 0xAA && cpu->ios[addr] == 0x55)
	{
          val = 0;
          /* COP reset here.  */
	}
      break;
      
    default:
      break;

    }
  cpu->ios[addr] = val;
}

static unsigned
m68hc11cpu_io_write_buffer (struct hw *me,
			    const void *source,
			    int space,
			    unsigned_word base,
			    unsigned nr_bytes)
{
  SIM_DESC sd;
  struct m68hc11cpu *controller = hw_data (me);
  unsigned byte;
  sim_cpu *cpu;
  int result;

  HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));

  sd = hw_system (me); 
  cpu = STATE_CPU (sd, 0);  

  if (base >= cpu->bank_start && base < cpu->bank_end)
    {
      address_word virt_addr = phys_to_virt (cpu, base);
      if (virt_addr != base)
        return sim_core_write_buffer (sd, cpu, space, source,
                                      virt_addr, nr_bytes);
    }
  base -= controller->attach_address;
  result = sim_core_write_buffer (sd, cpu,
				  io_map, source, base, nr_bytes);
  if (result > 0)
    return result;

  byte = 0;
  while (nr_bytes)
    {
      uint8 val;
      if (base >= controller->attach_size)
	break;

      val = *((uint8*) source);
      m68hc11cpu_io_write (me, cpu, base, val);
      source = (char*) source + 1;
      base++;
      byte++;
      nr_bytes--;
    }
  return byte;
}

const struct hw_descriptor dv_m68hc11_descriptor[] = {
  { "m68hc11", m68hc11cpu_finish },
  { "m68hc12", m68hc11cpu_finish },
  { NULL },
};