gencode.c

这个是LINUX下的GDB调度工具的源码

  { "emul",  "{ uint32 src1 = (uint32) cpu_get_d (proc);\
  uint32 src2 = (uint32) cpu_get_y (proc);\
  src1 *= src2;\
  cpu_set_d (proc, src1);\
  cpu_set_y (proc, src1 >> 16);\
  cpu_set_ccr_Z (proc, src1 == 0);\
  cpu_set_ccr_C (proc, src1 & 0x08000);\
  cpu_set_ccr_N (proc, src1 & 0x80000000);}" },
  { "emuls",  "cpu_special (proc, M6812_EMULS)" },
  { "mem",   "cpu_special (proc, M6812_MEM)" },
  { "rtc",   "cpu_special (proc, M6812_RTC)" },
  { "emacs", "cpu_special (proc, M6812_EMACS)" },
  { "idivs", "cpu_special (proc, M6812_IDIVS)" },
  { "edivs", "cpu_special (proc, M6812_EDIVS)" },
  { "exg8",  "cpu_exg (proc, src8)" },
  { "move8", "cpu_move8 (proc, op)" },
  { "move16","cpu_move16 (proc, op)" },

  { "max8",  "cpu_ccr_update_sub8 (proc, dst8 - src8, dst8, src8);\
              if (dst8 < src8) dst8 = src8" },
  { "min8",  "cpu_ccr_update_sub8 (proc, dst8 - src8, dst8, src8);\
              if (dst8 > src8) dst8 = src8" },
  { "max16", "cpu_ccr_update_sub16 (proc, dst16 - src16, dst16, src16);\
              if (dst16 < src16) dst16 = src16" },
  { "min16", "cpu_ccr_update_sub16 (proc, dst16 - src16, dst16, src16);\
              if (dst16 > src16) dst16 = src16" },

  { "rev",   "cpu_special (proc, M6812_REV);" },
  { "revw",  "cpu_special (proc, M6812_REVW);" },
  { "wav",   "cpu_special (proc, M6812_WAV);" },
  { "tbl8",  "cpu_special (proc, M6812_ETBL);" },
  { "tbl16", "cpu_special (proc, M6812_ETBL);" }
};

/* Definition of an opcode of the 68HC11.  */
struct m6811_opcode_def
{
  const char	 *name;
  const char	 *operands;
  const char	 *insn_pattern;
  unsigned char	 insn_size;
  unsigned char	 insn_code;
  unsigned char	 insn_min_cycles;
  unsigned char	 insn_max_cycles;
  unsigned char	 set_flags_mask;
  unsigned char	 clr_flags_mask;
  unsigned char	 chg_flags_mask;
};


/*
 *  { "dex", "x->x", "dec16", 1, 0x00, 5, _M,  CHG_NONE },
 * Name -+					 +----- Insn CCR changes
 * Operands  ---+			  +------------ Max # cycles
 * Pattern   -----------+	       +--------------- Min # cycles
 * Size	     -----------------+	  +-------------------- Opcode
 *
 * Operands   Fetch operand		Save result
 * -------    --------------		------------
 * x->x	      src16 = x			x = dst16
 * d->d	      src16 = d			d = dst16
 * b,a->a     src8 = b dst8 = a		a = dst8
 * sp->x      src16 = sp		x = dst16
 * (sp)->a    src8 = pop8		a = dst8
 * a->(sp)    src8 = a			push8 dst8
 * (x)->(x)   src8 = (IND, X)		(IND, X) = dst8
 * (y)->a     src8 = (IND, Y)		a = dst8
 * ()->b      src8 = (EXT)		b = dst8
 */
struct m6811_opcode_def m6811_page1_opcodes[] = {
  { "test", 0,		0,	     1, 0x00,  5, _M,  CHG_NONE },
  { "nop",  0,		0,	     1, 0x01,  2,  2,  CHG_NONE },
  { "idiv", "x,d->x",	"idiv16",    1, 0x02,  3, 41,  CLR_V_CHG_ZC},
  { "fdiv", "x,d->x",	"fdiv16",    1, 0x03,  3, 41,  CHG_ZVC},
  { "lsrd", "d->d",	"lsr16",     1, 0x04,  3,  3,  CLR_N_CHG_ZVC },
  { "asld", "d->d",	"lsl16",     1, 0x05,  3,  3,  CHG_NZVC },
  { "tap",  "a->ccr",	"mov8",	     1, 0x06,  2,  2,  CHG_ALL},
  { "tpa",  "ccr->a",	"mov8",	     1, 0x07,  2,  2,  CHG_NONE },
  { "inx",  "x->x",	"inc16",     1, 0x08,  3,  3,  CHG_Z },
  { "dex",  "x->x",	"dec16",     1, 0x09,  3,  3,  CHG_Z },
  { "clv",  0,		0,	     1, 0x0a,  2,  2,  CLR_V },
  { "sev",  0,		0,	     1, 0x0b,  2,  2,  SET_V },
  { "clc",  0,		0,	     1, 0x0c,  2,  2,  CLR_C },
  { "sec",  0,		0,	     1, 0x0d,  2,  2,  SET_C },
  { "cli",  0,		0,	     1, 0x0e,  2,  2,  CLR_I },
  { "sei",  0,		0,	     1, 0x0f,  2,  2,  SET_I },
  { "sba",  "b,a->a",	"sub8",	     1, 0x10,  2,  2,  CHG_NZVC },
  { "cba",  "b,a",	"sub8",	     1, 0x11,  2,  2,  CHG_NZVC },
  { "brset","*,#,r",	"brset8",    4, 0x12,  6,  6, CHG_NONE },
  { "brclr","*,#,r",	"brclr8",    4, 0x13,  6,  6, CHG_NONE },
  { "bset", "*,#->*",	"or8",	     3, 0x14,  6,  6, CLR_V_CHG_NZ },
  { "bclr", "*,#->*",	"bclr8",     3, 0x15,  6,  6, CLR_V_CHG_NZ },
  { "tab",  "a->b",	"movtst8",   1, 0x16,  2,  2, CLR_V_CHG_NZ },
  { "tba",  "b->a",	"movtst8",   1, 0x17,  2,  2, CLR_V_CHG_NZ },
  { "page2", 0,		"page2",     1, 0x18,  0,  0, CHG_NONE },
  { "page3", 0,		"page3",     1, 0x1a,  0,  0, CHG_NONE },

  /* After 'daa', the Z flag is undefined.  Mark it as changed.	 */
  { "daa",  "",	        "daa8",	     1, 0x19,  2,  2, CHG_NZVC },
  { "aba",  "b,a->a",	"add8",	     1, 0x1b,  2,  2, CHG_HNZVC},
  { "bset", "(x),#->(x)","or8",	     3, 0x1c,  7,  7, CLR_V_CHG_NZ },
  { "bclr", "(x),#->(x)","bclr8",    3, 0x1d,  7,  7, CLR_V_CHG_NZ },
  { "brset","(x),#,r",	"brset8",    4, 0x1e,  7,  7, CHG_NONE },
  { "brclr","(x),#,r",	"brclr8",    4, 0x1f,  7,  7, CHG_NONE },

  /* Relative branch.  All of them take 3 bytes.  Flags not changed.  */
  { "bra",  "r",	0,	     2, 0x20,  3,  3, CHG_NONE },
  { "brn",  "r",	"nop",	     2, 0x21,  3,  3, CHG_NONE },
  { "bhi",  "r",	0,	     2, 0x22,  3,  3, CHG_NONE },
  { "bls",  "r",	0,	     2, 0x23,  3,  3, CHG_NONE },
  { "bcc",  "r",	0,	     2, 0x24,  3,  3, CHG_NONE },
  { "bcs",  "r",	0,	     2, 0x25,  3,  3, CHG_NONE },
  { "bne",  "r",	0,	     2, 0x26,  3,  3, CHG_NONE },
  { "beq",  "r",	0,	     2, 0x27,  3,  3, CHG_NONE },
  { "bvc",  "r",	0,	     2, 0x28,  3,  3, CHG_NONE },
  { "bvs",  "r",	0,	     2, 0x29,  3,  3, CHG_NONE },
  { "bpl",  "r",	0,	     2, 0x2a,  3,  3, CHG_NONE },
  { "bmi",  "r",	0,	     2, 0x2b,  3,  3, CHG_NONE },
  { "bge",  "r",	0,	     2, 0x2c,  3,  3, CHG_NONE },
  { "blt",  "r",	0,	     2, 0x2d,  3,  3, CHG_NONE },
  { "bgt",  "r",	0,	     2, 0x2e,  3,  3, CHG_NONE },
  { "ble",  "r",	0,	     2, 0x2f,  3,  3, CHG_NONE },

  { "tsx",  "sp->x",	"tsxy16",    1, 0x30,  3,  3, CHG_NONE },
  { "ins",  "sp->sp",	"ins16",     1, 0x31,  3,  3, CHG_NONE },
  { "pula", "(sp)->a",	"mov8",	     1, 0x32,  4,  4, CHG_NONE },
  { "pulb", "(sp)->b",	"mov8",	     1, 0x33,  4,  4, CHG_NONE },
  { "des",  "sp->sp",	"des16",     1, 0x34,  3,  3, CHG_NONE },
  { "txs",  "x->sp",	"txys16",    1, 0x35,  3,  3, CHG_NONE },
  { "psha", "a->(sp)",	"mov8",	     1, 0x36,  3,  3, CHG_NONE },
  { "pshb", "b->(sp)",	"mov8",	     1, 0x37,  3,  3, CHG_NONE },
  { "pulx", "(sp)->x",	"mov16",     1, 0x38,  5,  5, CHG_NONE },
  { "rts",  0,		"rts11",     1, 0x39,  5,  5, CHG_NONE },
  { "abx",  "b,x->x",	"abxy16",    1, 0x3a,  3,  3, CHG_NONE },
  { "rti",  0,		"rti11",     1, 0x3b, 12, 12, CHG_ALL},
  { "pshx", "x->(sp)",	"mov16",     1, 0x3c,  4,  4, CHG_NONE },
  { "mul",  "b,a->d",	"mul16",     1, 0x3d,  3, 10, CHG_C },
  { "wai",  0,		0,	     1, 0x3e, 14, _M, CHG_NONE },
  { "swi",  0,		0,	     1, 0x3f, 14, _M, CHG_NONE },
  { "nega", "a->a",	"neg8",	     1, 0x40,  2,  2, CHG_NZVC },
  { "syscall", "",	"syscall",   1, 0x41,  2,  2, CHG_NONE },
  { "coma", "a->a",	"com8",	     1, 0x43,  2,  2, SET_C_CLR_V_CHG_NZ },
  { "lsra", "a->a",	"lsr8",	     1, 0x44,  2,  2, CLR_N_CHG_ZVC},
  { "rora", "a->a",	"ror8",	     1, 0x46,  2,  2, CHG_NZVC },
  { "asra", "a->a",	"asr8",	     1, 0x47,  2,  2, CHG_NZVC },
  { "asla", "a->a",	"lsl8",	     1, 0x48,  2,  2, CHG_NZVC },
  { "rola", "a->a",	"rol8",	     1, 0x49,  2,  2, CHG_NZVC },
  { "deca", "a->a",	"dec8",	     1, 0x4a,  2,  2, CHG_NZV },
  { "inca", "a->a",	"inc8",	     1, 0x4c,  2,  2, CHG_NZV },
  { "tsta", "a",	"tst8",	     1, 0x4d,  2,  2, CLR_V_CHG_NZ },
  { "clra", "->a",	"clr8",	     1, 0x4f,  2,  2, SET_Z_CLR_NVC },
  { "negb", "b->b",	"neg8",	     1, 0x50,  2,  2, CHG_NZVC },
  { "comb", "b->b",	"com8",	     1, 0x53,  2,  2, SET_C_CLR_V_CHG_NZ },
  { "lsrb", "b->b",	"lsr8",	     1, 0x54,  2,  2, CLR_N_CHG_ZVC },
  { "rorb", "b->b",	"ror8",	     1, 0x56,  2,  2, CHG_NZVC },
  { "asrb", "b->b",	"asr8",	     1, 0x57,  2,  2, CHG_NZVC },
  { "aslb", "b->b",	"lsl8",	     1, 0x58,  2,  2, CHG_NZVC },
  { "rolb", "b->b",	"rol8",	     1, 0x59,  2,  2, CHG_NZVC },
  { "decb", "b->b",	"dec8",	     1, 0x5a,  2,  2, CHG_NZV },
  { "incb", "b->b",	"inc8",	     1, 0x5c,  2,  2, CHG_NZV },
  { "tstb", "b",	"tst8",	     1, 0x5d,  2,  2, CLR_V_CHG_NZ },
  { "clrb", "->b",	"clr8",	     1, 0x5f,  2,  2, SET_Z_CLR_NVC },
  { "neg",  "(x)->(x)", "neg8",	     2, 0x60,  6,  6, CHG_NZVC },
  { "com",  "(x)->(x)", "com8",	     2, 0x63,  6,  6, SET_C_CLR_V_CHG_NZ },
  { "lsr",  "(x)->(x)", "lsr8",	     2, 0x64,  6,  6, CLR_N_CHG_ZVC },
  { "ror",  "(x)->(x)", "ror8",	     2, 0x66,  6,  6, CHG_NZVC },
  { "asr",  "(x)->(x)", "asr8",	     2, 0x67,  6,  6, CHG_NZVC },
  { "asl",  "(x)->(x)", "lsl8",	     2, 0x68,  6,  6, CHG_NZVC },
  { "rol",  "(x)->(x)", "rol8",	     2, 0x69,  6,  6, CHG_NZVC },
  { "dec",  "(x)->(x)", "dec8",	     2, 0x6a,  6,  6, CHG_NZV },
  { "inc",  "(x)->(x)", "inc8",	     2, 0x6c,  6,  6, CHG_NZV },
  { "tst",  "(x)",	"tst8",	     2, 0x6d,  6,  6, CLR_V_CHG_NZ },
  { "jmp",  "&(x)",	"bra",	     2, 0x6e,  3,  3, CHG_NONE },
  { "clr",  "->(x)",	"clr8",	     2, 0x6f,  6,  6, SET_Z_CLR_NVC },
  { "neg",  "()->()",	"neg8",	     3, 0x70,  6,  6, CHG_NZVC },
  { "com",  "()->()",	"com8",	     3, 0x73,  6,  6, SET_C_CLR_V_CHG_NZ },
  { "lsr",  "()->()",	"lsr8",	     3, 0x74,  6,  6, CLR_V_CHG_ZVC },
  { "ror",  "()->()",	"ror8",	     3, 0x76,  6,  6, CHG_NZVC },
  { "asr",  "()->()",	"asr8",	     3, 0x77,  6,  6, CHG_NZVC },
  { "asl",  "()->()",	"lsl8",	     3, 0x78,  6,  6, CHG_NZVC },
  { "rol",  "()->()",	"rol8",	     3, 0x79,  6,  6, CHG_NZVC },
  { "dec",  "()->()",	"dec8",	     3, 0x7a,  6,  6, CHG_NZV },
  { "inc",  "()->()",	"inc8",	     3, 0x7c,  6,  6, CHG_NZV },
  { "tst",  "()",	"tst8",	     3, 0x7d,  6,  6, CLR_V_CHG_NZ },
  { "jmp",  "&()",	"bra",	     3, 0x7e,  3,  3, CHG_NONE },
  { "clr",  "->()",	"clr8",	     3, 0x7f,  6,  6, SET_Z_CLR_NVC },
  { "suba", "#,a->a",	"sub8",	     2, 0x80,  2,  2, CHG_NZVC },
  { "cmpa", "#,a",	"sub8",	     2, 0x81,  2,  2, CHG_NZVC },
  { "sbca", "#,a->a",	"sbc8",	     2, 0x82,  2,  2, CHG_NZVC },
  { "subd", "#,d->d",	"sub16",     3, 0x83,  4,  4, CHG_NZVC },
  { "anda", "#,a->a",	"and8",	     2, 0x84,  2,  2, CLR_V_CHG_NZ },
  { "bita", "#,a",	"and8",	     2, 0x85,  2,  2, CLR_V_CHG_NZ },
  { "ldaa", "#->a",	"movtst8",   2, 0x86,  2,  2, CLR_V_CHG_NZ },
  { "eora", "#,a->a",	"eor8",	     2, 0x88,  2,  2, CLR_V_CHG_NZ },
  { "adca", "#,a->a",	"adc8",	     2, 0x89,  2,  2, CHG_HNZVC },
  { "oraa", "#,a->a",	"or8",	     2, 0x8a,  2,  2, CLR_V_CHG_NZ },
  { "adda", "#,a->a",	"add8",	     2, 0x8b,  2,  2, CHG_HNZVC },
  { "cmpx", "#,x",	"sub16",     3, 0x8c,  4,  4, CHG_NZVC },
  { "bsr",  "r",	"jsr_11_16", 2, 0x8d,  6,  6, CHG_NONE },
  { "lds",  "#->sp",	"movtst16",  3, 0x8e,  3,  3, CLR_V_CHG_NZ },
  { "xgdx", "x->x",	"xgdxy16",   1, 0x8f,  3,  3, CHG_NONE },
  { "suba", "*,a->a",	"sub8",	     2, 0x90,  3,  3, CHG_NZVC },
  { "cmpa", "*,a",	"sub8",	     2, 0x91,  3,  3, CHG_NZVC },
  { "sbca", "*,a->a",	"sbc8",	     2, 0x92,  3,  3, CHG_NZVC },
  { "subd", "*,d->d",	"sub16",     2, 0x93,  5,  5, CHG_NZVC },
  { "anda", "*,a->a",	"and8",	     2, 0x94,  3,  3, CLR_V_CHG_NZ },
  { "bita", "*,a",	"and8",	     2, 0x95,  3,  3, CLR_V_CHG_NZ },
  { "ldaa", "*->a",	"movtst8",   2, 0x96,  3,  3, CLR_V_CHG_NZ },
  { "staa", "a->*",	"movtst8",   2, 0x97,  3,  3, CLR_V_CHG_NZ },
  { "eora", "*,a->a",	"eor8",	     2, 0x98,  3,  3, CLR_V_CHG_NZ },
  { "adca", "*,a->a",	"adc8",	     2, 0x99,  3,  3, CHG_HNZVC },
  { "oraa", "*,a->a",	"or8",	     2, 0x9a,  3,  3, CLR_V_CHG_NZ },
  { "adda", "*,a->a",	"add8",	     2, 0x9b,  3,  3, CHG_HNZVC },
  { "cmpx", "*,x",	"sub16",     2, 0x9c,  5,  5, CHG_NZVC },
  { "jsr",  "*",	"jsr_11_16", 2, 0x9d,  5,  5, CHG_NONE },
  { "lds",  "*->sp",	"movtst16",  2, 0x9e,  4,  4, CLR_V_CHG_NZ },
  { "sts",  "sp->*",	"movtst16",  2, 0x9f,  4,  4, CLR_V_CHG_NZ },
  { "suba", "(x),a->a", "sub8",	     2, 0xa0,  4,  4, CHG_NZVC },
  { "cmpa", "(x),a",	"sub8",	     2, 0xa1,  4,  4, CHG_NZVC },
  { "sbca", "(x),a->a", "sbc8",	     2, 0xa2,  4,  4, CHG_NZVC },
  { "subd", "(x),d->d", "sub16",     2, 0xa3,  6,  6, CHG_NZVC },
  { "anda", "(x),a->a", "and8",	     2, 0xa4,  4,  4, CLR_V_CHG_NZ },
  { "bita", "(x),a",	"and8",	     2, 0xa5,  4,  4, CLR_V_CHG_NZ },
  { "ldaa", "(x)->a",	"movtst8",   2, 0xa6,  4,  4, CLR_V_CHG_NZ },
  { "staa", "a->(x)",	"movtst8",   2, 0xa7,  4,  4, CLR_V_CHG_NZ },
  { "eora", "(x),a->a", "eor8",	     2, 0xa8,  4,  4, CLR_V_CHG_NZ },
  { "adca", "(x),a->a", "adc8",	     2, 0xa9,  4,  4, CHG_HNZVC },
  { "oraa", "(x),a->a", "or8",	     2, 0xaa,  4,  4, CLR_V_CHG_NZ },
  { "adda", "(x),a->a", "add8",	     2, 0xab,  4,  4, CHG_HNZVC },
  { "cmpx", "(x),x",	"sub16",     2, 0xac,  6,  6, CHG_NZVC },
  { "jsr",  "&(x)",	"jsr_11_16", 2, 0xad,  6,  6, CHG_NONE },
  { "lds",  "(x)->sp",	"movtst16",  2, 0xae,  5,  5, CLR_V_CHG_NZ },
  { "sts",  "sp->(x)",	"movtst16",  2, 0xaf,  5,  5, CLR_V_CHG_NZ },
  { "suba", "(),a->a",	"sub8",	     3, 0xb0,  4,  4, CHG_NZVC },
  { "cmpa", "(),a",	"sub8",	     3, 0xb1,  4,  4, CHG_NZVC },
  { "sbca", "(),a->a",	"sbc8",	     3, 0xb2,  4,  4, CHG_NZVC },
  { "subd", "(),d->d",	"sub16",     3, 0xb3,  6,  6, CHG_NZVC },
  { "anda", "(),a->a",	"and8",	     3, 0xb4,  4,  4, CLR_V_CHG_NZ },
  { "bita", "(),a",	"and8",	     3, 0xb5,  4,  4, CLR_V_CHG_NZ },
  { "ldaa", "()->a",	"movtst8",   3, 0xb6,  4,  4, CLR_V_CHG_NZ },
  { "staa", "a->()",	"movtst8",   3, 0xb7,  4,  4, CLR_V_CHG_NZ },
  { "eora", "(),a->a",	"eor8",	     3, 0xb8,  4,  4, CLR_V_CHG_NZ },
  { "adca", "(),a->a",	"adc8",	     3, 0xb9,  4,  4, CHG_HNZVC },
  { "oraa", "(),a->a",	"or8",	     3, 0xba,  4,  4, CLR_V_CHG_NZ },
  { "adda", "(),a->a",	"add8",	     3, 0xbb,  4,  4, CHG_HNZVC },
  { "cmpx", "(),x",	"sub16",     3, 0xbc,  5,  5, CHG_NZVC },
  { "jsr",  "&()",	"jsr_11_16", 3, 0xbd,  6,  6, CHG_NONE },
  { "lds",  "()->sp",	"movtst16",  3, 0xbe,  5,  5, CLR_V_CHG_NZ },
  { "sts",  "sp->()",	"movtst16",  3, 0xbf,  5,  5, CLR_V_CHG_NZ },
  { "subb", "#,b->b",	"sub8",	     2, 0xc0,  2,  2, CHG_NZVC },
  { "cmpb", "#,b",	"sub8",	     2, 0xc1,  2,  2, CHG_NZVC },
  { "sbcb", "#,b->b",	"sbc8",	     2, 0xc2,  2,  2, CHG_NZVC },
  { "addd", "#,d->d",	"add16",     3, 0xc3,  4,  4, CHG_NZVC },
  { "andb", "#,b->b",	"and8",	     2, 0xc4,  2,  2, CLR_V_CHG_NZ },
  { "bitb", "#,b",	"and8",	     2, 0xc5,  2,  2, CLR_V_CHG_NZ },
  { "ldab", "#->b",	"movtst8",   2, 0xc6,  2,  2, CLR_V_CHG_NZ },
  { "eorb", "#,b->b",	"eor8",	     2, 0xc8,  2,  2, CLR_V_CHG_NZ },
  { "adcb", "#,b->b",	"adc8",	     2, 0xc9,  2,  2, CHG_HNZVC },
  { "orab", "#,b->b",	"or8",	     2, 0xca,  2,  2, CLR_V_CHG_NZ },
  { "addb", "#,b->b",	"add8",	     2, 0xcb,  2,  2, CHG_HNZVC },
  { "ldd",  "#->d",	"movtst16",  3, 0xcc,  3,  3, CLR_V_CHG_NZ },
  { "page4",0,		"page4",     1, 0xcd,  0,  0, CHG_NONE },
  { "ldx",  "#->x",	"movtst16",  3, 0xce,  3,  3, CLR_V_CHG_NZ },
  { "stop", 0,		0,	     1, 0xcf,  2,  2, CHG_NONE },
  { "subb", "*,b->b",	"sub8",	     2, 0xd0,  3,  3, CHG_NZVC },
  { "cmpb", "*,b",	"sub8",	     2, 0xd1,  3,  3, CHG_NZVC },
  { "sbcb", "*,b->b",	"sbc8",	     2, 0xd2,  3,  3, CHG_NZVC },
  { "addd", "*,d->d",	"add16",     2, 0xd3,  5,  5, CHG_NZVC },
  { "andb", "*,b->b",	"and8",	     2, 0xd4,  3,  3, CLR_V_CHG_NZ },
  { "bitb", "*,b",	"and8",	     2, 0xd5,  3,  3, CLR_V_CHG_NZ },
  { "ldab", "*->b",	"movtst8",   2, 0xd6,  3,  3, CLR_V_CHG_NZ },
  { "stab", "b->*",	"movtst8",   2, 0xd7,  3,  3, CLR_V_CHG_NZ },
  { "eorb", "*,b->b",	"eor8",	     2, 0xd8,  3,  3, CLR_V_CHG_NZ },
  { "adcb", "*,b->b",	"adc8",	     2, 0xd9,  3,  3, CHG_HNZVC },
  { "orab", "*,b->b",	"or8",	     2, 0xda,  3,  3, CLR_V_CHG_NZ },
  { "addb", "*,b->b",	"add8",	     2, 0xdb,  3,  3, CHG_HNZVC },
  { "ldd",  "*->d",	"movtst16",  2, 0xdc,  4,  4, CLR_V_CHG_NZ },
  { "std",  "d->*",	"movtst16",  2, 0xdd,  4,  4, CLR_V_CHG_NZ },
  { "ldx",  "*->x",	"movtst16",  2, 0xde,  4,  4, CLR_V_CHG_NZ },
  { "stx",  "x->*",	"movtst16",  2, 0xdf,  4,  4, CLR_V_CHG_NZ },
  { "subb", "(x),b->b", "sub8",	     2, 0xe0,  4,  4, CHG_NZVC },
  { "cmpb", "(x),b",	"sub8",	     2, 0xe1,  4,  4, CHG_NZVC },
  { "sbcb", "(x),b->b", "sbc8",	     2, 0xe2,  4,  4, CHG_NZVC },
  { "addd", "(x),d->d", "add16",     2, 0xe3,  6,  6, CHG_NZVC },
  { "andb", "(x),b->b", "and8",	     2, 0xe4,  4,  4, CLR_V_CHG_NZ },
  { "bitb", "(x),b",	"and8",	     2, 0xe5,  4,  4, CLR_V_CHG_NZ },
  { "ldab", "(x)->b",	"movtst8",   2, 0xe6,  4,  4, CLR_V_CHG_NZ },
  { "stab", "b->(x)",	"movtst8",   2, 0xe7,  4,  4, CLR_V_CHG_NZ },
  { "eorb", "(x),b->b", "eor8",	     2, 0xe8,  4,  4, CLR_V_CHG_NZ },