📄 igen.c
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case generate_calls: { gen_list *entry; for (entry = gen->tables; entry != NULL; entry = entry->next) { print_idecode_lookups (file, entry->table, cache_rules); /* output the main idecode routine */ if (!options.gen.icache) { print_idecode_issue_function_header (file, (options.gen.multi_sim ? entry->model->name : NULL), 1 /*is definition */ , 1 /*ALWAYS ONE WORD */ ); lf_printf (file, "{\n"); lf_indent (file, +2); lf_printf (file, "%sinstruction_address nia;\n", options.module.global.prefix.l); print_idecode_body (file, entry->table, "nia ="); lf_printf (file, "return nia;"); lf_indent (file, -2); lf_printf (file, "}\n"); } } break; } case generate_jumps: { lf_print__this_file_is_empty (file, "generating a jump engine"); break; } }}/****************************************************************/static voidgen_run_c (lf *file, gen_table *gen){ gen_list *entry; lf_printf (file, "#include \"sim-main.h\"\n"); lf_printf (file, "#include \"engine.h\"\n"); lf_printf (file, "#include \"idecode.h\"\n"); lf_printf (file, "#include \"bfd.h\"\n"); lf_printf (file, "\n"); if (options.gen.multi_sim) { print_idecode_issue_function_header (file, NULL, is_function_variable, 1); lf_printf (file, "\n"); print_engine_run_function_header (file, NULL, is_function_variable); lf_printf (file, "\n"); } lf_printf (file, "void\n"); lf_printf (file, "sim_engine_run (SIM_DESC sd,\n"); lf_printf (file, " int next_cpu_nr,\n"); lf_printf (file, " int nr_cpus,\n"); lf_printf (file, " int siggnal)\n"); lf_printf (file, "{\n"); lf_indent (file, +2); if (options.gen.multi_sim) { lf_printf (file, "int mach;\n"); lf_printf (file, "if (STATE_ARCHITECTURE (sd) == NULL)\n"); lf_printf (file, " mach = 0;\n"); lf_printf (file, "else\n"); lf_printf (file, " mach = STATE_ARCHITECTURE (sd)->mach;\n"); lf_printf (file, "switch (mach)\n"); lf_printf (file, " {\n"); lf_indent (file, +2); for (entry = gen->tables; entry != NULL; entry = entry->next) { if (options.gen.default_model != NULL && (strcmp (entry->model->name, options.gen.default_model) == 0 || strcmp (entry->model->full_name, options.gen.default_model) == 0)) lf_printf (file, "default:\n"); lf_printf (file, "case bfd_mach_%s:\n", entry->model->full_name); lf_indent (file, +2); print_function_name (file, "issue", NULL, /* format name */ NULL, /* NO processor */ NULL, /* expanded bits */ function_name_prefix_idecode); lf_printf (file, " = "); print_function_name (file, "issue", NULL, /* format name */ entry->model->name, NULL, /* expanded bits */ function_name_prefix_idecode); lf_printf (file, ";\n"); print_function_name (file, "run", NULL, /* format name */ NULL, /* NO processor */ NULL, /* expanded bits */ function_name_prefix_engine); lf_printf (file, " = "); print_function_name (file, "run", NULL, /* format name */ entry->model->name, NULL, /* expanded bits */ function_name_prefix_engine); lf_printf (file, ";\n"); lf_printf (file, "break;\n"); lf_indent (file, -2); } if (options.gen.default_model == NULL) { lf_printf (file, "default:\n"); lf_indent (file, +2); lf_printf (file, "sim_engine_abort (sd, NULL, NULL_CIA,\n"); lf_printf (file, " \"sim_engine_run - unknown machine\");\n"); lf_printf (file, "break;\n"); lf_indent (file, -2); } lf_indent (file, -2); lf_printf (file, " }\n"); } print_function_name (file, "run", NULL, /* format name */ NULL, /* NO processor */ NULL, /* expanded bits */ function_name_prefix_engine); lf_printf (file, " (sd, next_cpu_nr, nr_cpus, siggnal);\n"); lf_indent (file, -2); lf_printf (file, "}\n");}/****************************************************************/static gen_table *do_gen (insn_table *isa, decode_table *decode_rules){ gen_table *gen; if (decode_rules == NULL) error (NULL, "Must specify a decode table\n"); if (isa == NULL) error (NULL, "Must specify an instruction table\n"); if (decode_table_max_word_nr (decode_rules) > 0) options.gen.multi_word = decode_table_max_word_nr (decode_rules); gen = make_gen_tables (isa, decode_rules); gen_tables_expand_insns (gen); gen_tables_expand_semantics (gen); return gen;}/****************************************************************/igen_options options;intmain (int argc, char **argv, char **envp){ cache_entry *cache_rules = NULL; lf_file_references file_references = lf_include_references; decode_table *decode_rules = NULL; insn_table *isa = NULL; gen_table *gen = NULL; char *real_file_name = NULL; int is_header = 0; int ch; lf *standard_out = lf_open ("-", "stdout", lf_omit_references, lf_is_text, "igen"); INIT_OPTIONS (); if (argc == 1) { printf ("Usage:\n"); printf ("\n"); printf (" igen <config-opts> ... <input-opts>... <output-opts>...\n"); printf ("\n"); printf ("Config options:\n"); printf ("\n"); printf (" -B <bit-size>\n"); printf ("\t Set the number of bits in an instruction (deprecated).\n"); printf ("\t This option can now be set directly in the instruction table.\n"); printf ("\n"); printf (" -D <data-structure>\n"); printf ("\t Dump the specified data structure to stdout. Valid structures include:\n"); printf ("\t processor-names - list the names of all the processors (models)\n"); printf ("\n"); printf (" -F <filter-list>\n"); printf ("\t Filter out any instructions with a non-empty flags field that contains\n"); printf ("\t a flag not listed in the <filter-list>.\n"); printf ("\n"); printf (" -H <high-bit>\n"); printf ("\t Set the number of the high (most significant) instruction bit (deprecated).\n"); printf ("\t This option can now be set directly in the instruction table.\n"); printf ("\n"); printf (" -I <directory>\n"); printf ("\t Add <directory> to the list of directories searched when opening a file\n"); printf ("\n"); printf (" -M <model-list>\n"); printf ("\t Filter out any instructions that do not support at least one of the listed\n"); printf ("\t models (An instructions with no model information is considered to support\n"); printf ("\t all models.).\n"); printf ("\n"); printf (" -N <nr-cpus>\n"); printf ("\t Generate a simulator supporting <nr-cpus>\n"); printf ("\t Specify `-N 0' to disable generation of the SMP. Specifying `-N 1' will\n"); printf ("\t still generate an SMP enabled simulator but will only support one CPU.\n"); printf ("\n"); printf (" -T <mechanism>\n"); printf ("\t Override the decode mechanism specified by the decode rules\n"); printf ("\n"); printf (" -P <prefix>\n"); printf ("\t Prepend global names (except itable) with the string <prefix>.\n"); printf ("\t Specify -P <module>=<prefix> to set a specific <module>'s prefix.\n"); printf ("\n"); printf (" -S <suffix>\n"); printf ("\t Replace a global name (suffix) (except itable) with the string <suffix>.\n"); printf ("\t Specify -S <module>=<suffix> to change a specific <module>'s name (suffix).\n"); printf ("\n"); printf (" -Werror\n"); printf ("\t Make warnings errors\n"); printf (" -Wnodiscard\n"); printf ("\t Suppress warnings about discarded functions and instructions\n"); printf (" -Wnowidth\n"); printf ("\t Suppress warnings about instructions with invalid widths\n"); printf (" -Wnounimplemented\n"); printf ("\t Suppress warnings about unimplemented instructions\n"); printf ("\n"); printf (" -G [!]<gen-option>\n"); printf ("\t Any of the following options:\n"); printf ("\n"); printf ("\t decode-duplicate - Override the decode rules, forcing the duplication of\n"); printf ("\t semantic functions\n"); printf ("\t decode-combine - Combine any duplicated entries within a table\n"); printf ("\t decode-zero-reserved - Override the decode rules, forcing reserved bits to be\n"); printf ("\t treated as zero.\n"); printf ("\t decode-switch-is-goto - Overfide the padded-switch code type as a goto-switch\n"); printf ("\n"); printf ("\t gen-conditional-issue - conditionally issue each instruction\n"); printf ("\t gen-delayed-branch - need both cia and nia passed around\n"); printf ("\t gen-direct-access - use #defines to directly access values\n"); printf ("\t gen-zero-r<N> - arch assumes GPR(<N>) == 0, keep it that way\n"); printf ("\t gen-icache[=<N> - generate an instruction cracking cache of size <N>\n"); printf ("\t Default size is %d\n", options.gen.icache_size); printf ("\t gen-insn-in-icache - save original instruction when cracking\n"); printf ("\t gen-multi-sim[=MODEL] - generate multiple simulators - one per model\n"); printf ("\t If specified MODEL is made the default architecture.\n"); printf ("\t By default, a single simulator that will\n"); printf ("\t execute any instruction is generated\n"); printf ("\t gen-multi-word - generate code allowing for multi-word insns\n"); printf ("\t gen-semantic-icache - include semantic code in cracking functions\n"); printf ("\t gen-slot-verification - perform slot verification as part of decode\n"); printf ("\t gen-nia-invalid - NIA defaults to nia_invalid\n"); printf ("\t gen-nia-void - do not compute/return NIA\n"); printf ("\n"); printf ("\t trace-combine - report combined entries a rule application\n"); printf ("\t trace-entries - report entries after a rules application\n"); printf ("\t trace-rule-rejection - report each rule as rejected\n"); printf ("\t trace-rule-selection - report each rule as selected\n"); printf ("\t trace-insn-insertion - report each instruction as it is inserted into a decode table\n"); printf ("\t trace-rule-expansion - report each instruction as it is expanded (before insertion into a decode table)\n"); printf ("\t trace-all - enable all trace options\n"); printf ("\n"); printf ("\t field-widths - instruction formats specify widths (deprecated)\n"); printf ("\t By default, an instruction format specifies bit\n"); printf ("\t positions\n"); printf ("\t This option can now be set directly in the\n"); printf ("\t instruction table\n"); printf ("\t jumps - use jumps instead of function calls\n"); printf ("\t omit-line-numbers - do not include line number information in the output\n"); printf ("\n"); printf ("Input options:\n"); printf ("\n"); printf (" -k <cache-rules> (deprecated)\n"); printf (" -o <decode-rules>\n"); printf (" -i <instruction-table>\n"); printf ("\n"); printf ("Output options:\n"); printf ("\n"); printf (" -x Perform expansion (required)\n"); printf (" -n <real-name> Specify the real name of the next output file\n"); printf (" -h Generate the header (.h) file rather than the body (.c)\n"); printf (" -c <output-file> output icache\n"); printf (" -d <output-file> output idecode\n"); printf (" -e <output-file> output engine\n"); printf (" -f <output-file> output support functions\n"); printf (" -m <output-file> output model\n"); printf (" -r <output-file> output multi-sim run\n"); printf (" -s <output-file> output schematic\n"); printf (" -t <output-file> output itable\n"); } while ((ch = getopt (argc, argv, "B:D:F:G:H:I:M:N:P:T:W:o:k:i:n:hc:d:e:m:r:s:t:f:x")) != -1) { fprintf (stderr, " -%c ", ch); if (optarg) fprintf (stderr, "%s ", optarg); fprintf (stderr, "\\\n"); switch (ch) { case 'M': filter_parse (&options.model_filter, optarg); break; case 'D': if (strcmp (optarg, "processor-names")) { char *processor; for (processor = filter_next (options.model_filter, ""); processor != NULL; processor = filter_next (options.model_filter, processor)) lf_printf (standard_out, "%s\n", processor); } else error (NULL, "Unknown data structure %s, not dumped\n", optarg); break; case 'F': filter_parse (&options.flags_filter, optarg); break; case 'I': { table_include **dir = &options.include; while ((*dir) != NULL) dir = &(*dir)->next; (*dir) = ZALLOC (table_include); (*dir)->dir = strdup (optarg); } break; case 'B': options.insn_bit_size = a2i (optarg); if (options.insn_bit_size <= 0 || options.insn_bit_size > max_insn_bit_size) { error (NULL, "Instruction bitsize must be in range 1..%d\n", max_insn_bit_size); } if (options.hi_bit_nr != options.insn_bit_size - 1 && options.hi_bit_nr != 0) { error (NULL, "Conflict betweem hi-bit-nr and insn-bit-size\n"); } break; case 'H': options.hi_bit_nr = a2i (optarg); if (options.hi_bit_nr != options.insn_bit_size - 1 && options.hi_bit_nr != 0) { error (NULL, "Conflict between hi-bit-nr and insn-bit-size\n"); } break; case 'N': options.gen.smp = a2i (optarg); break; case 'P': case 'S': { igen_module *names; igen_name *name; char *chp; chp = strchr (optarg, '='); if (chp == NULL) { names = &options.module.global; chp = optarg; }
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