v850.igen

这个是LINUX下的GDB调度工具的源码

rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
*v850e
*v850e1
"mul <imm9>, r<reg2>, r<reg3>"
{
  COMPAT_2 (OP_24007E0 ());
}


// MULH
rrrrr!0,000111,RRRRR:I:::mulh
"mulh r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_E0 ());
}

rrrrr!0,010111,iiiii:II:::mulh
"mulh <imm5>, r<reg2>"
{
  COMPAT_1 (OP_2E0 ());
}



// MULHI
rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
"mulhi <uimm16>, r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_6E0 ());
}



// MULU
rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
*v850e
*v850e1
"mulu r<reg1>, r<reg2>, r<reg3>"
{
  COMPAT_2 (OP_22207E0 ());
}

rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
*v850e
*v850e1
"mulu <imm9>, r<reg2>, r<reg3>"
{
  COMPAT_2 (OP_24207E0 ());
}



// NOP
0000000000000000:I:::nop
"nop"
{
  /* do nothing, trace nothing */
}



// NOT
rrrrr,000001,RRRRR:I:::not
"not r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_20 ());
}



// NOT1
01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
"not1 <bit3>, <disp16>[r<reg1>]"
{
  COMPAT_2 (OP_47C0 ());
}

rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
*v850e
*v850e1
"not1 r<reg2>, r<reg1>"
{
  COMPAT_2 (OP_E207E0 ());
}



// OR
rrrrr,001000,RRRRR:I:::or
"or r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_100 ());
}



// ORI 
rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
"ori <uimm16>, r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_680 ());
}



// PREPARE
0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
*v850e
*v850e1
"prepare <list12>, <imm5>"
{
  int  i;
  SAVE_2;
  
  trace_input ("prepare", OP_PUSHPOP1, 0);
  
  /* Store the registers with lower number registers being placed at
     higher addresses.  */
  for (i = 0; i < 12; i++)
    if ((OP[3] & (1 << type1_regs[ i ])))
      {
	SP -= 4;
	store_mem (SP, 4, State.regs[ 20 + i ]);
      }
  
  SP -= (OP[3] & 0x3e) << 1;
  
  trace_output (OP_PUSHPOP1);
}


0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
*v850e
*v850e1
"prepare <list12>, <imm5>, sp"
{
  COMPAT_2 (OP_30780 ());
}

0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
*v850e
*v850e1
"prepare <list12>, <imm5>, <uimm16>"
{
  COMPAT_2 (OP_B0780 ());
}

0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
*v850e
*v850e1
"prepare <list12>, <imm5>, <uimm16>"
{
  COMPAT_2 (OP_130780 ());
}

0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
*v850e
*v850e1
"prepare <list12>, <imm5>, <uimm32>"
{
  COMPAT_2 (OP_1B0780 ());
}



// RETI
0000011111100000 + 0000000101000000:X:::reti
"reti"
{
  if ((PSW & PSW_EP))
    {
      nia = (EIPC & ~1);
      PSW = EIPSW;
    }
  else if ((PSW & PSW_NP))
    {
      nia = (FEPC & ~1);
      PSW = FEPSW;
    }
  else
    {
      nia = (EIPC & ~1);
      PSW = EIPSW;
    }
  TRACE_BRANCH1 (PSW);
}



// SAR
rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
"sar r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_A007E0 ());
}

rrrrr,010101,iiiii:II:::sar
"sar <imm5>, r<reg2>"
{
  COMPAT_1 (OP_2A0 ());
}



// SASF
rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
*v850e
*v850e1
"sasf %s<cccc>, r<reg2>"
{
  COMPAT_2 (OP_20007E0 ());
}




// SATADD
rrrrr!0,000110,RRRRR:I:::satadd
"satadd r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_C0 ());
}

rrrrr!0,010001,iiiii:II:::satadd
"satadd <imm5>, r<reg2>"
{
  COMPAT_1 (OP_220 ());
}



// SATSUB
rrrrr!0,000101,RRRRR:I:::satsub
"satsub r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_A0 ());
}



// SATSUBI
rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
"satsubi <simm16>, r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_660 ());
}



// SATSUBR
rrrrr!0,000100,RRRRR:I:::satsubr
"satsubr r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_80 ());
}



// SETF
rrrrr,1111110,cccc + 0000000000000000:IX:::setf
"setf %s<cccc>, r<reg2>"
{
  COMPAT_2 (OP_7E0 ());
}



// SET1
00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
"set1 <bit3>, <disp16>[r<reg1>]"
{
  COMPAT_2 (OP_7C0 ());
}

rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
*v850e
*v850e1
"set1 r<reg2>, [r<reg1>]"
{
  COMPAT_2 (OP_E007E0 ());
}



// SHL
rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
"shl r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_C007E0 ());
}

rrrrr,010110,iiiii:II:::shl
"shl <imm5>, r<reg2>"
{
  COMPAT_1 (OP_2C0 ());
}



// SHR
rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
"shr r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_8007E0 ());
}

rrrrr,010100,iiiii:II:::shr
"shr <imm5>, r<reg2>"
{
  COMPAT_1 (OP_280 ());
}



// SLD
rrrrr,0110,ddddddd:IV:::sld.b
"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
"sld.b <disp7>[ep], r<reg2>"
{
  unsigned32 addr = EP + disp7;
  unsigned32 result = load_mem (addr, 1);
  if (PSW & PSW_US)
    {
      GR[reg2] = result;
      TRACE_LD_NAME ("sld.bu", addr, result);
    }
  else
    {
      result = EXTEND8 (result);
      GR[reg2] = result;
      TRACE_LD (addr, result);
    }
}

rrrrr,1000,ddddddd:IV:::sld.h
"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
"sld.h <disp8>[ep], r<reg2>"
{
  unsigned32 addr = EP + disp8;
  unsigned32 result = load_mem (addr, 2);
  if (PSW & PSW_US)
    {
      GR[reg2] = result;
      TRACE_LD_NAME ("sld.hu", addr, result);
    }
  else
    {
      result = EXTEND16 (result);
      GR[reg2] = result;
      TRACE_LD (addr, result);
    }
}

rrrrr,1010,dddddd,0:IV:::sld.w
"sld.w <disp8>[ep], r<reg2>"
{
  unsigned32 addr = EP + disp8;
  unsigned32 result = load_mem (addr, 4);
  GR[reg2] = result;
  TRACE_LD (addr, result);
}

rrrrr!0,0000110,dddd:IV:::sld.bu
*v850e
*v850e1
"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
"sld.bu <disp4>[ep], r<reg2>"
{
  unsigned32 addr = EP + disp4;
  unsigned32 result = load_mem (addr, 1);
  if (PSW & PSW_US)
    {
      result = EXTEND8 (result);
      GR[reg2] = result;
      TRACE_LD_NAME ("sld.b", addr, result);
    }
  else
    {
      GR[reg2] = result;
      TRACE_LD (addr, result);
    }
}

rrrrr!0,0000111,dddd:IV:::sld.hu
*v850e
*v850e1
"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
"sld.hu <disp5>[ep], r<reg2>"
{
  unsigned32 addr = EP + disp5;
  unsigned32 result = load_mem (addr, 2);
  if (PSW & PSW_US)
    {
      result = EXTEND16 (result);
      GR[reg2] = result;
      TRACE_LD_NAME ("sld.h", addr, result);
    }
  else
    {
      GR[reg2] = result;
      TRACE_LD (addr, result);
    }
}

// SST
rrrrr,0111,ddddddd:IV:::sst.b
"sst.b r<reg2>, <disp7>[ep]"
{
  COMPAT_1 (OP_380 ());
}

rrrrr,1001,ddddddd:IV:::sst.h
"sst.h r<reg2>, <disp8>[ep]"
{
  COMPAT_1 (OP_480 ());
}

rrrrr,1010,dddddd,1:IV:::sst.w
"sst.w r<reg2>, <disp8>[ep]"
{
  COMPAT_1 (OP_501 ());
}

// ST
rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
"st.b r<reg2>, <disp16>[r<reg1>]"
{
  COMPAT_2 (OP_740 ());
}

rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
"st.h r<reg2>, <disp16>[r<reg1>]"
{
  COMPAT_2 (OP_760 ());
}

rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
"st.w r<reg2>, <disp16>[r<reg1>]"
{
  COMPAT_2 (OP_10760 ());
}

// STSR
rrrrr,111111,regID + 0000000001000000:IX:::stsr
"stsr s<regID>, r<reg2>"
{
  TRACE_ALU_INPUT1 (SR[regID]);
  GR[reg2] = SR[regID];
  TRACE_ALU_RESULT (GR[reg2]);
}

// SUB
rrrrr,001101,RRRRR:I:::sub
"sub r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_1A0 ());
}

// SUBR
rrrrr,001100,RRRRR:I:::subr
"subr r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_180 ());
}

// SWITCH
00000000010,RRRRR:I:::switch
*v850e
*v850e1
"switch r<reg1>"
{
  unsigned long adr;
  SAVE_1;
  trace_input ("switch", OP_REG, 0);
  adr = (cia + 2) + (State.regs[ reg1 ] << 1);
  nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
  trace_output (OP_REG);
}

// SXB
00000000101,RRRRR:I:::sxb
*v850e
*v850e1
"sxb r<reg1>"
{
  TRACE_ALU_INPUT1 (GR[reg1]);
  GR[reg1] = EXTEND8 (GR[reg1]);
  TRACE_ALU_RESULT (GR[reg1]);
}

// SXH
00000000111,RRRRR:I:::sxh
*v850e
*v850e1
"sxh r<reg1>"
{
  TRACE_ALU_INPUT1 (GR[reg1]);
  GR[reg1] = EXTEND16 (GR[reg1]);
  TRACE_ALU_RESULT (GR[reg1]);
}

// TRAP
00000111111,iiiii + 0000000100000000:X:::trap
"trap <vector>"
{
  COMPAT_2 (OP_10007E0 ());
}

// TST
rrrrr,001011,RRRRR:I:::tst
"tst r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_160 ());
}

// TST1
11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
"tst1 <bit3>, <disp16>[r<reg1>]"
{
  COMPAT_2 (OP_C7C0 ());
}

rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
*v850e
*v850e1
"tst1 r<reg2>, [r<reg1>]"
{
  COMPAT_2 (OP_E607E0 ());
}

// XOR
rrrrr,001001,RRRRR:I:::xor
"xor r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_120 ());
}

// XORI
rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
"xori <uimm16>, r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_6A0 ());
}

// ZXB
00000000100,RRRRR:I:::zxb
*v850e
*v850e1
"zxb r<reg1>"
{
  TRACE_ALU_INPUT1 (GR[reg1]);
  GR[reg1] = GR[reg1] & 0xff;
  TRACE_ALU_RESULT (GR[reg1]);
}

// ZXH
00000000110,RRRRR:I:::zxh
*v850e
*v850e1
"zxh r<reg1>"
{
  TRACE_ALU_INPUT1 (GR[reg1]);
  GR[reg1] = GR[reg1] & 0xffff;
  TRACE_ALU_RESULT (GR[reg1]);
}

// Right field must be zero so that it doesn't clash with DIVH
// Left field must be non-zero so that it doesn't clash with SWITCH
11111,000010,00000:I:::break
*v850
*v850e
{
  sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
}

11111,000010,00000:I:::dbtrap
*v850e1
"dbtrap"
{
  DBPC = cia + 2;
  DBPSW = PSW;
  PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
  PC = 0x00000060;
  nia = 0x00000060;
  TRACE_BRANCH0 ();
}

// New breakpoint: 0x7E0 0x7E0
00000,111111,00000 + 00000,11111,100000:X:::ilgop
{
  sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
}

// Return from debug trap: 0x146007e0
0000011111100000 + 0000000101000110:X:::dbret
*v850e1
"dbret"
{
  nia = DBPC;
  PSW = DBPSW;
  TRACE_BRANCH1 (PSW);
}