v850.igen

这个是LINUX下的GDB调度工具的源码

:option:::insn-bit-size:16
:option:::hi-bit-nr:15


:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
:option:::format-names:XI,XII,XIII
:option:::format-names:XIV,XV
:option:::format-names:Z


:model:::v850:v850:

:option:::multi-sim:true
:model:::v850e:v850e:
:option:::multi-sim:true
:model:::v850e1:v850e1:

// Cache macros

:cache:::unsigned:reg1:RRRRR:(RRRRR)
:cache:::unsigned:reg2:rrrrr:(rrrrr)
:cache:::unsigned:reg3:wwwww:(wwwww)

:cache:::unsigned:disp4:dddd:(dddd)
:cache:::unsigned:disp5:dddd:(dddd << 1)
:cache:::unsigned:disp7:ddddddd:ddddddd
:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
:cache:::unsigned:disp8:dddddd:(dddddd << 2)
:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)

:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
:cache:::unsigned:imm6:iiiiii:iiiiii
:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)

:cache:::unsigned:vector:iiiii:iiiii

:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)

:cache:::unsigned:bit3:bbb:bbb


// What do we do with an illegal instruction?
:internal::::illegal:
{
  sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
		  (unsigned long) cia);
  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
}



// Add

rrrrr,001110,RRRRR:I:::add
"add r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_1C0 ());
}

rrrrr,010010,iiiii:II:::add
"add <imm5>,r<reg2>"
{
  COMPAT_1 (OP_240 ());
}



// ADDI
rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
"addi <simm16>, r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_600 ());
}



// AND
rrrrr,001010,RRRRR:I:::and
"and r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_140 ());
}



// ANDI
rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
"andi <uimm16>, r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_6C0 ());
}



// Map condition code to a string
:%s::::cccc:int cccc
{
  switch (cccc)
    {
    case 0xf: return "gt";
    case 0xe: return "ge";
    case 0x6: return "lt";

    case 0x7: return "le";

    case 0xb: return "h";
    case 0x9: return "nl";
    case 0x1: return "l";

    case 0x3: return "nh";

    case 0x2: return "e";

    case 0xa: return "ne";

    case 0x0: return "v";
    case 0x8: return "nv";
    case 0x4: return "n";
    case 0xc: return "p";
      /* case 0x1: return "c"; */
      /* case 0x9: return "nc"; */
      /* case 0x2: return "z"; */
      /* case 0xa: return "nz"; */
    case 0x5: return "r"; /* always */
    case 0xd: return "sa";
    }
  return "(null)";
}


// Bcond
ddddd,1011,ddd,cccc:III:::Bcond
"b%s<cccc> <disp9>"
{
  int cond;
  if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
    // Special case - treat "br *" like illegal instruction
    sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
  } else {
    cond = condition_met (cccc);
    if (cond)
      nia = cia + disp9;
    TRACE_BRANCH1 (cond);
  }
}



// BSH
rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
*v850e
*v850e1
"bsh r<reg2>, r<reg3>"
{
  unsigned32 value;
  TRACE_ALU_INPUT1 (GR[reg2]);

  value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
	   | MOVED32 (GR[reg2], 31, 24, 23, 16)
	   | MOVED32 (GR[reg2], 7, 0, 15, 8)
	   | MOVED32 (GR[reg2], 15, 8, 7, 0));

  GR[reg3] = value;
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
  if (value == 0) PSW |= PSW_Z;
  if (value & 0x80000000) PSW |= PSW_S;
  if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;

  TRACE_ALU_RESULT (GR[reg3]);
}

// BSW
rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
*v850e
*v850e1
"bsw r<reg2>, r<reg3>"
{
#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
  unsigned32 value;
  TRACE_ALU_INPUT1 (GR[reg2]);

  value = GR[reg2];
  value >>= 24;
  value |= (GR[reg2] << 24);
  value |= ((GR[reg2] << 8) & 0x00ff0000);
  value |= ((GR[reg2] >> 8) & 0x0000ff00);
  GR[reg3] = value;

  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);

  if (value == 0) PSW |= PSW_Z;
  if (value & 0x80000000) PSW |= PSW_S;
  if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;

  TRACE_ALU_RESULT (GR[reg3]);
}

// CALLT
0000001000,iiiiii:II:::callt
*v850e
*v850e1
"callt <imm6>"
{
  unsigned32 adr;
  unsigned32 off;
  CTPC  = cia + 2;
  CTPSW = PSW;
  adr = (CTBP & ~1) + (imm6 << 1);
  off = load_mem (adr, 2) & ~1; /* Force alignment */
  nia = (CTBP & ~1) + off;
  TRACE_BRANCH3 (adr, CTBP, off);
}


// CLR1
10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
"clr1 <bit3>, <disp16>[r<reg1>]"
{
  COMPAT_2 (OP_87C0 ());
}

rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
*v850e
*v850e1
"clr1 r<reg2>, [r<reg1>]"
{
  COMPAT_2 (OP_E407E0 ());
}


// CTRET
0000011111100000 + 0000000101000100:X:::ctret
*v850e
*v850e1
"ctret"
{
  nia  = (CTPC & ~1);
  PSW = (CTPSW & (CPU)->psw_mask);
  TRACE_BRANCH1 (PSW);
}

// CMOV
rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
*v850e
*v850e1
"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
{
  int cond = condition_met (cccc);
  TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
  GR[reg3] = cond ? GR[reg1] : GR[reg2];
  TRACE_ALU_RESULT (GR[reg3]);
}

rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
*v850e
*v850e1
"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
{
  int cond = condition_met (cccc);
  TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
  GR[reg3] = cond ? imm5 : GR[reg2];
  TRACE_ALU_RESULT (GR[reg3]);
}

// CMP
rrrrr,001111,RRRRR:I:::cmp
"cmp r<reg1>, r<reg2>"
{
  COMPAT_1 (OP_1E0 ());
}

rrrrr,010011,iiiii:II:::cmp
"cmp <imm5>, r<reg2>"
{
  COMPAT_1 (OP_260 ());
}



// DI
0000011111100000 + 0000000101100000:X:::di
"di"
{
  COMPAT_2 (OP_16007E0 ());
}



// DISPOSE
// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
// "dispose <imm5>, <list12>"
0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
*v850e
*v850e1
"dispose <imm5>, <list12>":RRRRR == 0
"dispose <imm5>, <list12>, [reg1]"
{
  int i;
  SAVE_2;
      
  trace_input ("dispose", OP_PUSHPOP1, 0);

  SP += (OP[3] & 0x3e) << 1;

  /* Load the registers with lower number registers being retrieved
     from higher addresses.  */
  for (i = 12; i--;)
    if ((OP[3] & (1 << type1_regs[ i ])))
      {
	State.regs[ 20 + i ] = load_mem (SP, 4);
	SP += 4;
      }
  
  if ((OP[3] & 0x1f0000) != 0)
    {
      nia = State.regs[ (OP[3] >> 16) & 0x1f];
    }
  
  trace_output (OP_PUSHPOP1);
}


// DIV
rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
*v850e
*v850e1
"div r<reg1>, r<reg2>, r<reg3>"
{
  COMPAT_2 (OP_2C007E0 ());
}


// DIVH
rrrrr!0,000010,RRRRR!0:I:::divh
"divh r<reg1>, r<reg2>"
{
  unsigned32 ov, s, z;
  signed long int op0, op1, result;

  trace_input ("divh", OP_REG_REG, 0);

  PC = cia;
  OP[0] = instruction_0 & 0x1f;
  OP[1] = (instruction_0 >> 11) & 0x1f;

  /* Compute the result.  */
  op0 = EXTEND16 (State.regs[OP[0]]);
  op1 = State.regs[OP[1]];
  
  if (op0 == 0xffffffff && op1 == 0x80000000)
    {
      result = 0x80000000;
      ov = 1;
    }
  else if (op0 != 0)
    {
      result = op1 / op0;
      ov = 0;
    }
  else
    {
      result = 0x0;
      ov = 1;
    }
  
  /* Compute the condition codes.  */
  z = (result == 0);
  s = (result & 0x80000000);
  
  /* Store the result and condition codes.  */
  State.regs[OP[1]] = result;
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));

  trace_output (OP_REG_REG);

  PC += 2;
  nia = PC;
}

rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
*v850e
*v850e1
"divh r<reg1>, r<reg2>, r<reg3>"
{
  COMPAT_2 (OP_28007E0 ());
}


// DIVHU
rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
*v850e
*v850e1
"divhu r<reg1>, r<reg2>, r<reg3>"
{
  COMPAT_2 (OP_28207E0 ());
}


// DIVU
rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
*v850e
*v850e1
"divu r<reg1>, r<reg2>, r<reg3>"
{
  COMPAT_2 (OP_2C207E0 ());
}


// EI
1000011111100000 + 0000000101100000:X:::ei
"ei"
{
  COMPAT_2 (OP_16087E0 ());
}



// HALT
0000011111100000 + 0000000100100000:X:::halt
"halt"
{
  COMPAT_2 (OP_12007E0 ());
}



// HSW
rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
*v850e
*v850e1
"hsw r<reg2>, r<reg3>"
{
  unsigned32 value;
  TRACE_ALU_INPUT1 (GR[reg2]);

  value = GR[reg2];
  value >>= 16;
  value |= (GR[reg2] << 16);
  
  GR[reg3] = value;

  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);

  if (value == 0) PSW |= PSW_Z;
  if (value & 0x80000000) PSW |= PSW_S;
  if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;

  TRACE_ALU_RESULT (GR[reg3]);
}



// JARL
rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
"jarl <disp22>, r<reg2>"
{
  GR[reg2] = nia;
  nia = cia + disp22;
  TRACE_BRANCH1 (GR[reg2]);
}



// JMP
00000000011,RRRRR:I:::jmp
"jmp [r<reg1>]"
{
  nia = GR[reg1] & ~1;
  TRACE_BRANCH0 ();
}



// JR
0000011110,dddddd + ddddddddddddddd,0:V:::jr
"jr <disp22>"
{
  nia = cia + disp22;
  TRACE_BRANCH0 ();
}



// LD
rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
"ld.b <disp16>[r<reg1>], r<reg2>"
{
  COMPAT_2 (OP_700 ());
}

rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
"ld.h <disp16>[r<reg1>], r<reg2>"
{
  COMPAT_2 (OP_720 ());
}

rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
"ld.w <disp16>[r<reg1>], r<reg2>"
{
  COMPAT_2 (OP_10720 ());
}

rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
*v850e
*v850e1
"ld.bu <disp16>[r<reg1>], r<reg2>"
{
  COMPAT_2 (OP_10780 ());
}

rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
*v850e
*v850e1
"ld.hu <disp16>[r<reg1>], r<reg2>"
{
  COMPAT_2 (OP_107E0 ());
}


// LDSR
regID,111111,RRRRR + 0000000000100000:IX:::ldsr
"ldsr r<reg1>, s<regID>"
{
  TRACE_ALU_INPUT1 (GR[reg1]);
  
  if (&PSW == &SR[regID])
    PSW = (GR[reg1] & (CPU)->psw_mask);
  else
    SR[regID] = GR[reg1];
  
  TRACE_ALU_RESULT (SR[regID]);
}



// MOV
rrrrr!0,000000,RRRRR:I:::mov
"mov r<reg1>, r<reg2>"
{
  TRACE_ALU_INPUT0 ();
  GR[reg2] = GR[reg1];
  TRACE_ALU_RESULT (GR[reg2]);
}


rrrrr!0,010000,iiiii:II:::mov
"mov <imm5>, r<reg2>"
{
  COMPAT_1 (OP_200 ());
}

00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
*v850e
*v850e1
"mov <imm32>, r<reg1>"
{
  SAVE_2;
  trace_input ("mov", OP_IMM_REG, 4);
  State.regs[ OP[0] ] = load_mem (PC + 2, 4);
  trace_output (OP_IMM_REG);
}



// MOVEA
rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
"movea <simm16>, r<reg1>, r<reg2>"
{
  TRACE_ALU_INPUT2 (GR[reg1], simm16);
  GR[reg2] = GR[reg1] + simm16;
  TRACE_ALU_RESULT (GR[reg2]);
}



// MOVHI
rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
"movhi <uimm16>, r<reg1>, r<reg2>"
{
  COMPAT_2 (OP_640 ());
}



// MUL
rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
*v850e
*v850e1
"mul r<reg1>, r<reg2>, r<reg3>"
{
  COMPAT_2 (OP_22007E0 ());
}