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📁 这个是LINUX下的GDB调度工具的源码
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2002-07-13  Andrew Cagney  <ac131313@redhat.com>	* cpu.h: Mark file obsolete.	* sim-main.h,  sim-calls.c, engine.c, cpu.c, alu.h: Ditto.	* dc-short, ic-d30v, d30v-insns, Makefile.in: Ditto.2002-06-16  Andrew Cagney  <ac131313@redhat.com>	* configure: Regenerated to track ../common/aclocal.m4 changes.2000-07-05  Nick Clifton  <nickc@cygnus.com>	* d30v-insns: Change minimum loop size limit to 0x10.Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>	* configure: Regenerated to track ../common/aclocal.m4 changes.2000-04-12  Frank Ch. Eigler  <fche@redhat.com>	* cpu.h (GPR_CLEAR): New macro.		(GPR_SET): Removed macro.Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>	* configure: Regenerated to track ../common/aclocal.m4 changes.Wed Sep  1 11:38:21 1999  Andrew Cagney  <cagney@b1.cygnus.com>	* d30v-insns: Cast CIA to LONG in printfs.Tue Aug 31 01:32:22 1999  Andrew Cagney  <cagney@b1.cygnus.com>	* cpu.h (unqueue_writes): Add declaration.1999-05-27  Michael Meissner  <meissner@cygnus.com>	* d30v-insns (do_repeat): Print a warning if a REPEAT or REPEATI	instruction loop is too small.1999-05-08  Felix Lee  <flee@cygnus.com>	* configure: Regenerated to track ../common/aclocal.m4 changes.	1999-03-16  Martin Hunt  <hunt@cygnus.com>	From Frank Ch. Eigler  <fche@cygnus.com>        * cpu.h (mvtsys_left_p): New flag for MVTSYS instruction history.        * d30v-insns (mvtsys): Set this flag instead of left_kills_right_p.        (do_sath): Detect MVTSYS by new flag.        * engine.c (unqueue_writes): Detect MVTSYS by new flag.        (do_2_short, do_parallel): Initialize new flag.       1999-02-26  Frank Ch. Eigler  <fche@cygnus.com>	* tconfig.in (SIM_HANDLES_LMA): Make it so.1999-01-12  Frank Ch. Eigler  <fche@cygnus.com>	* engine.c (unqueue_writes): Make PSW conflict resolution code 	conditional - disable it for MVTSYS || insn case.	1999-01-11  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_sath): Drain PSW write queue before PSW_S_FLAG 	update.	* engine.c (unqueue_writes): Make non-static.  Remove PSW_V/VA	special case.	(do_parallel): Don't drain PSW write queue for MVTSYS || insn.1999-01-07  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_ld2h): Sign-extend loaded half-words.1999-01-05  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_ld2h): Read memory in word units.	(do_ld4bh): Ditto.  Correct sign extension.	(do_ld4bhu): Ditto.	(do_st2h): Write memory in word units.	(do_st4hb): Ditto.	(st4hb): Correct mnemonic in igen template.1998-12-08  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns: (do_ld2h): Don't update R0 nor R1 for double-word insn.	(do_ld2w): Ditto. 	(do_ld4bh): Ditto. 	(do_ld4bhu): Ditto. 	(do_mulx2h): Ditto.1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_repeat): Don't set RP for repeat count 1.1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_src): Treat shift count -32 naturally instead of	producing zero result.1998-11-22  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_src): Limit SRC shift count to -32 .. 31.1998-11-16  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (dbt): Defer PSW/DPSW update with new DID_TRAP code 2.  	* engine.c (unqueue_writes): Perform DBT processing on PSW/DPSW here.1998-11-12  Frank Ch. Eigler  <fche@cygnus.com>	* cpu.h (_sim_cpu): Removed is_delayed_call field, and associated 	RPT_IS_CALL macro.  	* sim-calls.c (sim_create_inferior): Don't initialize is_delayed_call.	* d30v-insns (do_dbra): Don't clear RPT_IS_CALL. (do_dbrai): Ditto. 	(do_djmp): Ditto. (do_djmpi): Ditto. (do_repeat): Ditto. 	* d30v-insns (do_dbsr): Don't set RPT_IS_CALL, but set R62 instead. 	(do_dbsri): Ditto. (do_djsr): Dito. (do_djsri): Ditto.	* engine.c (sim_engine_run): Remove conditional setting of R62 based 	upon RPT_IS_CALL.	1998-11-08  Frank Ch. Eigler  <fche@cygnus.com>	* sim-calls.c (sim_open): Add dummy memory range over control	register region (0x40000000..0x4000FFFF). 1998-11-06  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_mvfacc): Use loop to limit shift count to 63 .. 0.Tue Oct 13 11:01:16 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_sra,do_srah,do_srl,do_srlh): Make shift 	count -32 to produce zero result.	(do_src): Ditto for shift count == -64.Mon Oct 12 23:04:11 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (ROT): Use 0x1f bit mask for rotate count masking.	(do_sra,do_srl): Use loop to limit shift count to -32 .. 31.	(do_srah,do_srlh): Use loop to limit shift count to -32 .. 31.	(sra2h,srl2h): Use loop to limit shift count to -16 .. 15.	(do_src): Use loop to limit shift count to -64 .. 63.Fri Oct  9 16:46:52 1998  Doug Evans  <devans@canuck.cygnus.com>	* sim-calls.c (get_insn_name): New fn.	(sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.	* sim-main.h (MAX_INSNS,INSN_NAME): Delete.Mon Sep 28 10:43:28 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_sra,do_srah,do_srl,do_srlh,ROT,do_src): Use	correct MSB bit numbers for sign extension masks.Fri Sep 25 17:32:27 1998  Frank Ch. Eigler  <fche@cygnus.com>	* engine.c (do_parallel): Unqueue writes if MU instruction was	a MVTSYS, as identified by its left_kills_right_p side-effect.Fri Sep 25 12:31:34 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_sra,do_srah,do_srl,do_srlh,ROT,do_src): Mask 	shift/rotate counts to number of bits in width of operand; no 	longer saturate at maxima.Tue Jul 14 18:39:23 1998  Frank Ch. Eigler  <fche@cygnus.com>	* cpu.h (left_kills_right_p): New flag for non-branch instructions	that, when executed in left slot of a -> sequential pair, kill the	right slot.	* d30v-insns (mvtsys): Set flag for PSW/PSWh/PSWl/FLAG operands.	* engine.c (do_2_short): Respect flag.	Thu Jun  4 16:48:58 1998  David Taylor  <taylor@texas.cygnus.com>	* d30v-insns (do_trap): don't save the bPSW and PSW based on	current values because an instruction done in parallel with	the trap might change them, instead set a flag do that	unqueue_writes will take care of it.	* engine.c (unqueue_writes): finish trap handling	* cpu.h (_sim_cpu): add new field did_trap and a macro DID_TRAP	to make use of it; set by do_trap, tested and cleared by	unqueue_writes.Tue May 19 16:07:04 1998  Frank Ch. Eigler  <fche@cygnus.com>	* engine.c (unqueue_writes): Suppress the all enqueued writes to 	the same flags in PSW except the last.Fri May 15 11:38:59 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (RETI): Correct instruction spelling to "reit".Thu May 14 09:34:20 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (dbt): Handle DBT at end of repeat block.	(do_trap, dbt): Clear PSW_RP if at end of repeat block.Thu May 14 07:41:41 1998  Frank Ch. Eigler  <fche@cygnus.com>	* engine.c (sim_engine_run): Trigger DDBT based on previous PC, 	instead of next PC.Wed May 13 11:03:40 1998  Frank Ch. Eigler  <fche@cygnus.com>	* engine.c (sim_engine_run): Move DDBT handling after instruction 	decode/execute stage.Tue May 12 12:14:53 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_sat*): Correct "saturate to 0 bits" patch to 	properly handle negative saturation inputs.Tue May 12 11:11:26 1998  Frank Ch. Eigler  <fche@cygnus.com>	* engine.c (sim_engine_run): Decrement RPT_C only under more 	restricted conditions.Mon May 11 17:33:46 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_sat*): Make "saturate to 0 bits" pass through data 	unchanged.Mon May 11 16:27:04 1998  Frank Ch. Eigler  <fche@cygnus.com>	* engine.c (sim_engine_run): Implement DDBT (debugger debug trap)	functionality.Fri May  8 16:44:19 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_trap): Set bPC to RPT_S if trap is last	instruction in repeat block.	(bsr*/jsr*): Set R62 (LINK) to RPT_S if subroutine branch	is last instruction in repeat block.Fri May  8 11:06:50 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_sath): Query/update F4/PSW_S using proper flag 	macro.	* cpu.h (PSW_S_FLAG): New flag number for PSW_S status bit.Wed May  6 19:40:56 1998  Doug Evans  <devans@canuck.cygnus.com>	* sim-main.h (INSN_NAME): New arg `cpu'.Fri May  1 14:24:30 1998  Andrew Cagney  <cagney@b1.cygnus.com>	* d30v-insns: Fix parameter list to sim_engine_abort.Thu Apr 30 14:28:00 1998  Fred Fish  <fnf@cygnus.com>	* d30v-insns (do_sath): Add additional argument that determines	whether or not the F4 (PSW_S) bit in the PSW is updated.	(SAT2H): Do not update PSW_S bit.	(SATHp): Do update PSW_S bit.Tue Apr 28 23:36:00 1998  Fred Fish  <fnf@cygnus.com>	* d30v-insns (SRAHp, SRLHp):  Immediate values are signed 6 bit	values, not 5 bit values.Wed Apr 29 12:57:55 1998  Frank Ch. Eigler  <fche@cygnus.com>	* d30v-insns (do_incr): Check modular arithmetic limits after 	postincrement/postdecrement, rather than before, to match 	erroneous hardware behavior.Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>        * configure: Regenerated to track ../common/aclocal.m4 changes.Mon Apr 27 19:42:00 1998  Fred Fish  <fnf@cygnus.com>	* d30v-insns (do_trap): Clear all bits in PSW except SM and DB.Mon Apr 27 14:55:00 1998  Fred Fish  <fnf@cygnus.com>	* d30v-insns (do_mulx2h): Low order results go in ra+1, high	order in ra.Mon Apr 27 14:42:00 1998  Fred Fish  <fnf@cygnus.com>	* d30v-insns (do_mulx2h): Rewrite to do proper 32 bit signed	multiply of high and low fields from operands.Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>	* configure: Regenerated to track ../common/aclocal.m4 changes.	* config.in: Ditto.Sun Apr 26 15:20:20 1998  Tom Tromey  <tromey@cygnus.com>	* acconfig.h: New file.	* configure.in: Reverted change of Apr 24; use sinclude again.Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>	* configure: Regenerated to track ../common/aclocal.m4 changes.	* config.in: Ditto.Fri Apr 24 11:20:00 1998  Tom Tromey  <tromey@cygnus.com>	* configure.in: Don't call sinclude.Wed Apr 22 21:23:00 1998  Fred Fish  <fnf@cygnus.com>	* ic-d30v (RbU, RcU): Unsigned versions of Rb and Rc.	* d30v-insns (MVTACC): Use new RbU and RcU macros.Wed Apr 22 20:52:00 1998  Fred Fish  <fnf@cygnus.com>	* ic-d30v (RbHU,RbLU): Unsigned versions of RbH and RbL.	* d30v-insns (SRL2H): Use new RbHU and RbLU macros instead of	RbH and RbL.Mon Apr 13 16:59:00 1998  Fred Fish  <fnf@cygnus.com>	* d30v-insns (do_srl): Avoid undefined behavior of host compiler	when shifting left by more than 31 bits.Tue Apr  7 18:09:00 1998  Fred Fish  <fnf@cygnus.com>	* engine.c (sim_engine_run): Remove at_loop_end variable. Add	rp_was_set and rpt_c_was_nonzero variables.  Major restructuring of	code before and after instruction execution to properly handle state	of the RP bit in the PSW, the value in RPT_C, and other loop related	problems.Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>	* configure: Regenerated to track ../common/aclocal.m4 changes.Fri Apr  3 15:26:00 1998  Fred Fish  <fnf@cygnus.com>	* d30v-insns (do_trap): Use offset from EIT_VB rather than hardcoded	BASE_ADDRESS constant.	* cpu.h (BASE_ADDRESS): Remove constant not used any longer.Fri Apr  3 14:42:00 1998  Fred Fish  <fnf@cygnus.com>	* cpu.h (EIT_VB): Define macro to access EIT_VB register.	(EIT_VB_DEFAULT): Define value of EIT_VB register after reset.	* sim-calls.c (sim_create_inferior): Set EIT_VB to EIT_VB_DEFAULT.Tue Mar 31 19:00:00 1998  Fred Fish <fnf@cygnus.com>	* d30v-insns (do_dbrai): RPT_S is cia plus pcdisp rather than

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