engine.c

这个是LINUX下的GDB调度工具的源码

/* OBSOLETE   STATE_CPU (sd, 0)->unit = unit; */
/* OBSOLETE   STATE_CPU (sd, 0)->left_kills_right_p = 0; */
/* OBSOLETE   STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
/* OBSOLETE   nia = s_idecode_issue(sd, */
/* OBSOLETE 			insn1, */
/* OBSOLETE 			cia); */
/* OBSOLETE  */
/* OBSOLETE   unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
/* OBSOLETE  */
/* OBSOLETE   /* Only do the second instruction if the PC has not changed */ */
/* OBSOLETE   if ((nia == INVALID_INSTRUCTION_ADDRESS) && */
/* OBSOLETE       (! STATE_CPU (sd, 0)->left_kills_right_p)) { */
/* OBSOLETE     STATE_CPU (sd, 0)->unit = any_unit; */
/* OBSOLETE     nia = s_idecode_issue (sd, */
/* OBSOLETE 			   insn2, */
/* OBSOLETE 			   cia); */
/* OBSOLETE  */
/* OBSOLETE     unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
/* OBSOLETE   } */
/* OBSOLETE  */
/* OBSOLETE   STATE_CPU (sd, 0)->left_kills_right_p = 0; */
/* OBSOLETE   STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
/* OBSOLETE   return nia; */
/* OBSOLETE } */
/* OBSOLETE  */
/* OBSOLETE static address_word */
/* OBSOLETE do_parallel (SIM_DESC sd, */
/* OBSOLETE 	     s_instruction_word left_insn, */
/* OBSOLETE 	     s_instruction_word right_insn, */
/* OBSOLETE 	     address_word cia) */
/* OBSOLETE { */
/* OBSOLETE   address_word nia_left; */
/* OBSOLETE   address_word nia_right; */
/* OBSOLETE   address_word nia; */
/* OBSOLETE  */
/* OBSOLETE   /* run the first instruction */ */
/* OBSOLETE   STATE_CPU (sd, 0)->unit = memory_unit; */
/* OBSOLETE   STATE_CPU (sd, 0)->left_kills_right_p = 0; */
/* OBSOLETE   STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
/* OBSOLETE   nia_left = s_idecode_issue(sd, */
/* OBSOLETE 			     left_insn, */
/* OBSOLETE 			     cia); */
/* OBSOLETE  */
/* OBSOLETE   /* run the second instruction */ */
/* OBSOLETE   STATE_CPU (sd, 0)->unit = integer_unit; */
/* OBSOLETE   nia_right = s_idecode_issue(sd, */
/* OBSOLETE 			      right_insn, */
/* OBSOLETE 			      cia); */
/* OBSOLETE  */
/* OBSOLETE   /* merge the PC's */ */
/* OBSOLETE   if (nia_left == INVALID_INSTRUCTION_ADDRESS) { */
/* OBSOLETE     if (nia_right == INVALID_INSTRUCTION_ADDRESS) */
/* OBSOLETE       nia = INVALID_INSTRUCTION_ADDRESS; */
/* OBSOLETE     else */
/* OBSOLETE       nia = nia_right; */
/* OBSOLETE   } */
/* OBSOLETE   else { */
/* OBSOLETE     if (nia_right == INVALID_INSTRUCTION_ADDRESS) */
/* OBSOLETE       nia = nia_left; */
/* OBSOLETE     else { */
/* OBSOLETE       sim_engine_abort (sd, STATE_CPU (sd, 0), cia, "parallel jumps"); */
/* OBSOLETE       nia = INVALID_INSTRUCTION_ADDRESS; */
/* OBSOLETE     } */
/* OBSOLETE   } */
/* OBSOLETE  */
/* OBSOLETE   unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
/* OBSOLETE   return nia; */
/* OBSOLETE } */
/* OBSOLETE  */
/* OBSOLETE  */
/* OBSOLETE typedef enum { */
/* OBSOLETE   p_insn = 0, */
/* OBSOLETE   long_insn = 3, */
/* OBSOLETE   l_r_insn = 1, */
/* OBSOLETE   r_l_insn = 2, */
/* OBSOLETE } instruction_types; */
/* OBSOLETE  */
/* OBSOLETE STATIC_INLINE instruction_types */
/* OBSOLETE instruction_type(l_instruction_word insn) */
/* OBSOLETE { */
/* OBSOLETE   int fm0 = MASKED64(insn, 0, 0) != 0; */
/* OBSOLETE   int fm1 = MASKED64(insn, 32, 32) != 0; */
/* OBSOLETE   return ((fm0 << 1) | fm1); */
/* OBSOLETE } */
/* OBSOLETE  */
/* OBSOLETE  */
/* OBSOLETE  */
/* OBSOLETE void */
/* OBSOLETE sim_engine_run (SIM_DESC sd, */
/* OBSOLETE 		int last_cpu_nr, */
/* OBSOLETE 		int nr_cpus, */
/* OBSOLETE 		int siggnal) */
/* OBSOLETE { */
/* OBSOLETE   while (1) */
/* OBSOLETE     { */
/* OBSOLETE       address_word cia = PC; */
/* OBSOLETE       address_word nia; */
/* OBSOLETE       l_instruction_word insn = IMEM(cia); */
/* OBSOLETE       int rp_was_set; */
/* OBSOLETE       int rpt_c_was_nonzero; */
/* OBSOLETE  */
/* OBSOLETE       /* Before executing the instruction, we need to test whether or */
/* OBSOLETE 	 not RPT_C is greater than zero, and save that state for use */
/* OBSOLETE 	 after executing the instruction.  In particular, we need to */
/* OBSOLETE 	 not care whether the instruction changes RPT_C itself. */ */
/* OBSOLETE  */
/* OBSOLETE       rpt_c_was_nonzero = (RPT_C > 0); */
/* OBSOLETE  */
/* OBSOLETE       /* Before executing the instruction, we need to check to see if */
/* OBSOLETE 	 we have to decrement RPT_C, the repeat count register.  Do this */
/* OBSOLETE 	 if PC == RPT_E, but only if we are in an active repeat block. */ */
/* OBSOLETE  */
/* OBSOLETE       if (PC == RPT_E && */
/* OBSOLETE 	  (RPT_C > 0 || PSW_VAL (PSW_RP) != 0)) */
/* OBSOLETE 	{ */
/* OBSOLETE 	  RPT_C --; */
/* OBSOLETE 	} */
/* OBSOLETE        */
/* OBSOLETE       /* Now execute the instruction at PC */ */
/* OBSOLETE  */
/* OBSOLETE       switch (instruction_type (insn)) */
/* OBSOLETE 	{ */
/* OBSOLETE 	case long_insn: */
/* OBSOLETE 	  nia = do_long (sd, insn, cia); */
/* OBSOLETE 	  break; */
/* OBSOLETE 	case r_l_insn: */
/* OBSOLETE 	  /* L <- R */ */
/* OBSOLETE 	  nia = do_2_short (sd, insn, insn >> 32, integer_unit, cia); */
/* OBSOLETE 	  break; */
/* OBSOLETE 	case l_r_insn: */
/* OBSOLETE 	  /* L -> R */ */
/* OBSOLETE 	  nia = do_2_short (sd, insn >> 32, insn, memory_unit, cia); */
/* OBSOLETE 	  break; */
/* OBSOLETE 	case p_insn: */
/* OBSOLETE 	  nia = do_parallel (sd, insn >> 32, insn, cia); */
/* OBSOLETE 	  break; */
/* OBSOLETE 	default: */
/* OBSOLETE 	  sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */
/* OBSOLETE 			    "internal error - engine_run_until_stop - bad switch"); */
/* OBSOLETE 	  nia = -1; */
/* OBSOLETE 	} */
/* OBSOLETE  */
/* OBSOLETE       if (TRACE_ACTION) */
/* OBSOLETE 	{ */
/* OBSOLETE 	  if (TRACE_ACTION & TRACE_ACTION_CALL) */
/* OBSOLETE 	    call_occurred (sd, STATE_CPU (sd, 0), cia, nia); */
/* OBSOLETE  */
/* OBSOLETE 	  if (TRACE_ACTION & TRACE_ACTION_RETURN) */
/* OBSOLETE 	    return_occurred (sd, STATE_CPU (sd, 0), cia, nia); */
/* OBSOLETE  */
/* OBSOLETE 	  TRACE_ACTION = 0; */
/* OBSOLETE 	} */
/* OBSOLETE  */
/* OBSOLETE       /* Check now to see if we need to reset the RP bit in the PSW. */
/* OBSOLETE 	 There are three conditions for this, the RP bit is already */
/* OBSOLETE 	 set (just a speed optimization), the instruction we just */
/* OBSOLETE 	 executed is the last instruction in the loop, and the repeat */
/* OBSOLETE 	 count is currently zero. */ */
/* OBSOLETE  */
/* OBSOLETE       rp_was_set = PSW_VAL (PSW_RP); */
/* OBSOLETE       if (rp_was_set && (PC == RPT_E) && RPT_C == 0) */
/* OBSOLETE 	{ */
/* OBSOLETE 	  PSW_SET (PSW_RP, 0); */
/* OBSOLETE 	} */
/* OBSOLETE  */
/* OBSOLETE       /* Now update the PC.  If we just executed a jump instruction, */
/* OBSOLETE 	 that takes precedence over everything else.  Next comes */
/* OBSOLETE 	 branching back to RPT_S as a result of a loop.  Finally, the */
/* OBSOLETE 	 default is to simply advance to the next inline */
/* OBSOLETE 	 instruction. */ */
/* OBSOLETE  */
/* OBSOLETE       if (nia != INVALID_INSTRUCTION_ADDRESS) */
/* OBSOLETE 	{ */
/* OBSOLETE 	  PC = nia; */
/* OBSOLETE 	} */
/* OBSOLETE       else if (rp_was_set && rpt_c_was_nonzero && (PC == RPT_E)) */
/* OBSOLETE 	{ */
/* OBSOLETE 	  PC = RPT_S; */
/* OBSOLETE 	} */
/* OBSOLETE       else */
/* OBSOLETE 	{ */
/* OBSOLETE 	  PC = cia + 8; */
/* OBSOLETE 	} */
/* OBSOLETE  */
/* OBSOLETE       /* Check for DDBT (debugger debug trap) condition.  Do this after */
/* OBSOLETE 	 the repeat block checks so the excursion to the trap handler does */
/* OBSOLETE 	 not alter looping state. */ */
/* OBSOLETE  */
/* OBSOLETE       if (cia == IBA && PSW_VAL (PSW_DB)) */
/* OBSOLETE 	{ */
/* OBSOLETE 	  DPC = PC; */
/* OBSOLETE 	  PSW_SET (PSW_EA, 1); */
/* OBSOLETE 	  DPSW = PSW; */
/* OBSOLETE 	  /* clear all bits in PSW except SM */ */
/* OBSOLETE 	  PSW &= BIT32 (PSW_SM); */
/* OBSOLETE 	  /* add DS bit */ */
/* OBSOLETE 	  PSW |= BIT32 (PSW_DS); */
/* OBSOLETE 	  /* dispatch to DDBT handler */ */
/* OBSOLETE 	  PC = 0xfffff128; /* debugger_debug_trap_address */ */
/* OBSOLETE 	} */
/* OBSOLETE  */
/* OBSOLETE       /* process any events */ */
/* OBSOLETE       /* FIXME - should L->R or L<-R insns count as two cycles? */ */
/* OBSOLETE       if (sim_events_tick (sd)) */
/* OBSOLETE 	{ */
/* OBSOLETE 	  sim_events_process (sd); */
/* OBSOLETE 	} */
/* OBSOLETE     }   */
/* OBSOLETE } */
/* OBSOLETE  */
/* OBSOLETE  */
/* OBSOLETE /* d30v external interrupt handler. */
/* OBSOLETE  */
/* OBSOLETE    Note: This should be replaced by a proper interrupt delivery */
/* OBSOLETE    mechanism.  This interrupt mechanism discards later interrupts if */
/* OBSOLETE    an earlier interrupt hasn't been delivered. */
/* OBSOLETE  */
/* OBSOLETE    Note: This interrupt mechanism does not reset its self when the */
/* OBSOLETE    simulator is re-opened. */ */
/* OBSOLETE  */
/* OBSOLETE void */
/* OBSOLETE d30v_interrupt_event (SIM_DESC sd, */
/* OBSOLETE 		      void *data) */
/* OBSOLETE { */
/* OBSOLETE   if (PSW_VAL (PSW_IE)) */
/* OBSOLETE     /* interrupts not masked */ */
/* OBSOLETE     { */
/* OBSOLETE       /* scrub any pending interrupt */ */
/* OBSOLETE       if (sd->pending_interrupt != NULL) */
/* OBSOLETE 	sim_events_deschedule (sd, sd->pending_interrupt); */
/* OBSOLETE       /* deliver */ */
/* OBSOLETE       bPSW = PSW; */
/* OBSOLETE       bPC = PC; */
/* OBSOLETE       PSW = 0; */
/* OBSOLETE       PC = 0xfffff138; /* external interrupt */ */
/* OBSOLETE       do_stack_swap (sd); */
/* OBSOLETE     } */
/* OBSOLETE   else if (sd->pending_interrupt == NULL) */
/* OBSOLETE     /* interrupts masked and no interrupt pending */ */
/* OBSOLETE     { */
/* OBSOLETE       sd->pending_interrupt = sim_events_schedule (sd, 1, */
/* OBSOLETE 						   d30v_interrupt_event, */
/* OBSOLETE 						   data); */
/* OBSOLETE     } */
/* OBSOLETE } */
/* OBSOLETE  */
/* OBSOLETE #endif */