profile-fr400.c

这个是LINUX下的GDB调度工具的源码

{
  int cycles;
  INT dual_FRi;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0, 0};
  int *fr;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ps = CPU_PROFILE_STATE (cpu);
  dual_FRi = DUAL_REG (in_FRi);

  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 13-8 in the LSI.  */
  if (use_is_fp_load (cpu, in_FRi))
    {
      busy_adjustment[0] = 1;
      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
    }
  else
    enforce_full_fr_latency (cpu, in_FRi);
  if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi))
    {
      busy_adjustment[1] = 1;
      decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
    }
  else
    enforce_full_fr_latency (cpu, dual_FRi);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, dual_FRi);
  post_wait_for_FR (cpu, out_FRk);

  /* Restore the busy cycles of the registers we used.  */
  fr = ps->fr_busy;
  fr[in_FRi] += busy_adjustment[0];
  if (dual_FRi >= 0)
    fr[dual_FRi] += busy_adjustment[1];

  /* The latency of the output register will be at least the latency of the
     other inputs.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);

  /* Once initiated, post-processing has no latency.  */
  update_FR_ptime (cpu, out_FRk, 0);

  return cycles;
}

int
frvbf_model_fr400_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
				  int unit_num, int referenced,
				  INT in_FRi, INT in_FRj,
				  INT out_FRk)
{
  /* Modelling is the same as media unit 1.  */
  return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced,
					   in_FRi, in_FRj, out_FRk);
}

int
frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
			     int unit_num, int referenced,
			     INT in_ACC40Si, INT in_FRj,
			     INT out_ACC40Sk, INT out_FRk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  const CGEN_INSN *insn;
  int busy_adjustment[] = {0};
  int *fr;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ps = CPU_PROFILE_STATE (cpu);
  insn = idesc->idata;

  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 13-8 in the LSI.  */
  if (in_FRj >= 0)
    {
      if (use_is_fp_load (cpu, in_FRj))
	{
	  busy_adjustment[0] = 1;
	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
	}
      else
	enforce_full_fr_latency (cpu, in_FRj);
    }

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_ACC (cpu, in_ACC40Si);
  post_wait_for_ACC (cpu, out_ACC40Sk);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, out_FRk);

  /* Restore the busy cycles of the registers we used.  */
  fr = ps->fr_busy;

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  if (out_FRk >= 0)
    {
      update_FR_latency (cpu, out_FRk, ps->post_wait);
      update_FR_ptime (cpu, out_FRk, 1);
      /* Mark this use of the register as media unit 4.  */
      set_use_is_media_p4 (cpu, out_FRk);
    }
  else if (out_ACC40Sk >= 0)
    {
      update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait);
      update_ACC_ptime (cpu, out_ACC40Sk, 1);
      /* Mark this use of the register as media unit 4.  */
      set_acc_use_is_media_p4 (cpu, out_ACC40Sk);
    }

  return cycles;
}

int
frvbf_model_fr400_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
				  int unit_num, int referenced,
				  INT in_ACCGi, INT in_FRinti,
				  INT out_ACCGk, INT out_FRintk)
{
  /* Modelling is the same as media-4 unit except use accumulator guards
     as input instead of accumulators.  */
  return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced,
				      in_ACCGi, in_FRinti,
				      out_ACCGk, out_FRintk);
}

int
frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
				      int unit_num, int referenced,
				      INT in_ACC40Si, INT out_FRk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  const CGEN_INSN *insn;
  INT ACC40Si_1;
  INT FRk_1;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ps = CPU_PROFILE_STATE (cpu);
  ACC40Si_1 = DUAL_REG (in_ACC40Si);
  FRk_1 = DUAL_REG (out_FRk);

  insn = idesc->idata;

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_ACC (cpu, in_ACC40Si);
  post_wait_for_ACC (cpu, ACC40Si_1);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_FR (cpu, FRk_1);

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  if (out_FRk >= 0)
    {
      update_FR_latency (cpu, out_FRk, ps->post_wait);
      update_FR_ptime (cpu, out_FRk, 1);
      /* Mark this use of the register as media unit 4.  */
      set_use_is_media_p4 (cpu, out_FRk);
    }
  if (FRk_1 >= 0)
    {
      update_FR_latency (cpu, FRk_1, ps->post_wait);
      update_FR_ptime (cpu, FRk_1, 1);
      /* Mark this use of the register as media unit 4.  */
      set_use_is_media_p4 (cpu, FRk_1);
    }

  return cycles;
}

int
frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
			     int unit_num, int referenced,
			     INT in_FRi, INT out_FRk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  const CGEN_INSN *insn;
  int busy_adjustment[] = {0};
  int *fr;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ps = CPU_PROFILE_STATE (cpu);
  insn = idesc->idata;

  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 13-8 in the LSI.  */
  if (in_FRi >= 0)
    {
      if (use_is_fp_load (cpu, in_FRi))
	{
	  busy_adjustment[0] = 1;
	  decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
	}
      else
	enforce_full_fr_latency (cpu, in_FRi);
    }

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, out_FRk);

  /* Restore the busy cycles of the registers we used.  */
  fr = ps->fr_busy;
  if (in_FRi >= 0)
    fr[in_FRi] += busy_adjustment[0];

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  if (out_FRk >= 0)
    {
      update_FR_latency (cpu, out_FRk, ps->post_wait);
      update_FR_ptime (cpu, out_FRk, 1);

      /* Mark this use of the register as media unit 1.  */
      set_use_is_media_p6 (cpu, out_FRk);
    }

  return cycles;
}

int
frvbf_model_fr400_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
			     int unit_num, int referenced,
			     INT in_FRinti, INT in_FRintj,
			     INT out_FCCk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0, 0};
  int *fr;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);

  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 13-8 in the LSI.  */
  if (in_FRinti >= 0)
    {
      if (use_is_fp_load (cpu, in_FRinti))
	{
	  busy_adjustment[0] = 1;
	  decrease_FR_busy (cpu, in_FRinti, busy_adjustment[0]);
	}
      else
	enforce_full_fr_latency (cpu, in_FRinti);
    }
  if (in_FRintj >= 0 && in_FRintj != in_FRinti)
    {
      if (use_is_fp_load (cpu, in_FRintj))
	{
	  busy_adjustment[1] = 1;
	  decrease_FR_busy (cpu, in_FRintj, busy_adjustment[1]);
	}
      else
	enforce_full_fr_latency (cpu, in_FRintj);
    }

  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRinti);
  post_wait_for_FR (cpu, in_FRintj);
  post_wait_for_CCR (cpu, out_FCCk);

  /* Restore the busy cycles of the registers we used.  */
  fr = ps->fr_busy;
  if (in_FRinti >= 0)
    fr[in_FRinti] += busy_adjustment[0];
  if (in_FRintj >= 0)
    fr[in_FRintj] += busy_adjustment[1];

  /* The latency of FCCi_2 will be the latency of the other inputs plus 1
     cycle.  */
  update_CCR_latency (cpu, out_FCCk, ps->post_wait + 1);

  return cycles;
}

int
frvbf_model_fr400_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
				       int unit_num, int referenced,
				       INT in_FRi,
				       INT out_FRk)
{
  /* Insns using this unit are media-3 class insns, with a dual FRk output.  */
  int cycles;
  INT dual_FRk;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0};
  int *fr;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* If the previous use of the registers was a media op,
     then their latency will be less than previously recorded.
     See Table 13-13 in the LSI.  */
  dual_FRk = DUAL_REG (out_FRk);
  ps = CPU_PROFILE_STATE (cpu);
  if (use_is_fp_load (cpu, in_FRi))
    {
      busy_adjustment[0] = 1;
      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
    }
  else
    enforce_full_fr_latency (cpu, in_FRi);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_FR (cpu, dual_FRk);

  /* Restore the busy cycles of the registers we used.  */
  fr = ps->fr_busy;
  fr[in_FRi] += busy_adjustment[0];

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing has no latency.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_ptime (cpu, out_FRk, 0);

  if (dual_FRk >= 0)
    {
      update_FR_latency (cpu, dual_FRk, ps->post_wait);
      update_FR_ptime (cpu, dual_FRk, 0);
    }

  return cycles;
}

int
frvbf_model_fr400_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
				     int unit_num, int referenced,
				     INT in_FRj,
				     INT out_FRk)
{
  /* Insns using this unit are media-3 class insns, with a dual FRj input.  */
  int cycles;
  INT dual_FRj;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0, 0};
  int *fr;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* If the previous use of the registers was a media op,
     then their latency will be less than previously recorded.
     See Table 13-13 in the LSI.  */
  dual_FRj = DUAL_REG (in_FRj);
  ps = CPU_PROFILE_STATE (cpu);
  if (use_is_fp_load (cpu, in_FRj))
    {
      busy_adjustment[0] = 1;
      decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
    }
  else
    enforce_full_fr_latency (cpu, in_FRj);
  if (dual_FRj >= 0)
    {
      if (use_is_fp_load (cpu, dual_FRj))
	{
	  busy_adjustment[1] = 1;
	  decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]);
	}
      else
	enforce_full_fr_latency (cpu, dual_FRj);
    }

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, dual_FRj);
  post_wait_for_FR (cpu, out_FRk);

  /* Restore the busy cycles of the registers we used.  */
  fr = ps->fr_busy;
  fr[in_FRj] += busy_adjustment[0];
  if (dual_FRj >= 0)
    fr[dual_FRj] += busy_adjustment[1];

  /* The latency of the output register will be at least the latency of the
     other inputs.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);

  /* Once initiated, post-processing has no latency.  */
  update_FR_ptime (cpu, out_FRk, 0);

  return cycles;
}

int
frvbf_model_fr400_u_ici (SIM_CPU *cpu, const IDESC *idesc,
			 int unit_num, int referenced,
			 INT in_GRi, INT in_GRj)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced,
				  in_GRi, in_GRj);
}

int
frvbf_model_fr400_u_dci (SIM_CPU *cpu, const IDESC *idesc,
			 int unit_num, int referenced,
			 INT in_GRi, INT in_GRj)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced,
				  in_GRi, in_GRj);
}

int
frvbf_model_fr400_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
			 int unit_num, int referenced,
			 INT in_GRi, INT in_GRj)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced,
				  in_GRi, in_GRj);
}

int
frvbf_model_fr400_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
			  int unit_num, int referenced,
			  INT in_GRi, INT in_GRj)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced,
				   in_GRi, in_GRj);
}

int
frvbf_model_fr400_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
			  int unit_num, int referenced,
			  INT in_GRi, INT in_GRj)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced,
				   in_GRi, in_GRj);
}

int
frvbf_model_fr400_u_icul (SIM_CPU *cpu, const IDESC *idesc,
			  int unit_num, int referenced,
			  INT in_GRi, INT in_GRj)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced,
				   in_GRi, in_GRj);
}

int
frvbf_model_fr400_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
			  int unit_num, int referenced,
			  INT in_GRi, INT in_GRj)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced,
				   in_GRi, in_GRj);
}

int
frvbf_model_fr400_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
			     int unit_num, int referenced)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);
}

int
frvbf_model_fr400_u_membar (SIM_CPU *cpu, const IDESC *idesc,
			    int unit_num, int referenced)
{
  /* Modelling for this unit is the same as for fr500.  */
  return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);
}

#endif /* WITH_PROFILE_MODEL_P */