profile-fr400.c

这个是LINUX下的GDB调度工具的源码

	}
      if (ACC40Uk_1 >= 0)
	{
	  if (acc_use_is_media_p2 (cpu, ACC40Uk_1))
	    {
	      busy_adjustment[5] = 1;
	      decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]);
	    }
	}
      if (ACC40Uk_2 >= 0)
	{
	  if (acc_use_is_media_p2 (cpu, ACC40Uk_2))
	    {
	      busy_adjustment[6] = 1;
	      decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]);
	    }
	}
      if (ACC40Uk_3 >= 0)
	{
	  if (acc_use_is_media_p2 (cpu, ACC40Uk_3))
	    {
	      busy_adjustment[7] = 1;
	      decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]);
	    }
	}
    }

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, dual_FRi);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, dual_FRj);
  post_wait_for_ACC (cpu, out_ACC40Sk);
  post_wait_for_ACC (cpu, ACC40Sk_1);
  post_wait_for_ACC (cpu, ACC40Sk_2);
  post_wait_for_ACC (cpu, ACC40Sk_3);
  post_wait_for_ACC (cpu, out_ACC40Uk);
  post_wait_for_ACC (cpu, ACC40Uk_1);
  post_wait_for_ACC (cpu, ACC40Uk_2);
  post_wait_for_ACC (cpu, ACC40Uk_3);

  /* Restore the busy cycles of the registers we used.  */
  fr = ps->fr_busy;
  acc = ps->acc_busy;
  fr[in_FRi] += busy_adjustment[0];
  if (dual_FRi >= 0)
    fr[dual_FRi] += busy_adjustment[1];
  fr[in_FRj] += busy_adjustment[2];
  if (dual_FRj > 0)
    fr[dual_FRj] += busy_adjustment[3];
  if (out_ACC40Sk >= 0)
    {
      acc[out_ACC40Sk] += busy_adjustment[4];
      if (ACC40Sk_1 >= 0)
	acc[ACC40Sk_1] += busy_adjustment[5];
      if (ACC40Sk_2 >= 0)
	acc[ACC40Sk_2] += busy_adjustment[6];
      if (ACC40Sk_3 >= 0)
	acc[ACC40Sk_3] += busy_adjustment[7];
    }
  else if (out_ACC40Uk >= 0)
    {
      acc[out_ACC40Uk] += busy_adjustment[4];
      if (ACC40Uk_1 >= 0)
	acc[ACC40Uk_1] += busy_adjustment[5];
      if (ACC40Uk_2 >= 0)
	acc[ACC40Uk_2] += busy_adjustment[6];
      if (ACC40Uk_3 >= 0)
	acc[ACC40Uk_3] += busy_adjustment[7];
    }

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  if (out_ACC40Sk >= 0)
    {
      update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);

      set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
      if (ACC40Sk_1 >= 0)
	{
	  update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);

	  set_acc_use_is_media_p2 (cpu, ACC40Sk_1);
	}
      if (ACC40Sk_2 >= 0)
	{
	  update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);

	  set_acc_use_is_media_p2 (cpu, ACC40Sk_2);
	}
      if (ACC40Sk_3 >= 0)
	{
	  update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);

	  set_acc_use_is_media_p2 (cpu, ACC40Sk_3);
	}
    }
  else if (out_ACC40Uk >= 0)
    {
      update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);

      set_acc_use_is_media_p2 (cpu, out_ACC40Uk);
      if (ACC40Uk_1 >= 0)
	{
	  update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1);

	  set_acc_use_is_media_p2 (cpu, ACC40Uk_1);
	}
      if (ACC40Uk_2 >= 0)
	{
	  update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1);

	  set_acc_use_is_media_p2 (cpu, ACC40Uk_2);
	}
      if (ACC40Uk_3 >= 0)
	{
	  update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1);

	  set_acc_use_is_media_p2 (cpu, ACC40Uk_3);
	}
    }

  return cycles;
}

int
frvbf_model_fr400_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
				 int unit_num, int referenced,
				 INT in_ACC40Si, INT out_ACC40Sk)
{
  int cycles;
  INT ACC40Si_1;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0, 0, 0};
  int *acc;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ACC40Si_1 = DUAL_REG (in_ACC40Si);

  ps = CPU_PROFILE_STATE (cpu);
  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 13-8 in the LSI.  */
  if (acc_use_is_media_p2 (cpu, in_ACC40Si))
    {
      busy_adjustment[0] = 1;
      decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]);
    }
  if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1))
    {
      busy_adjustment[1] = 1;
      decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]);
    }
  if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1
      && acc_use_is_media_p2 (cpu, out_ACC40Sk))
    {
      busy_adjustment[2] = 1;
      decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
    }

  /* The post processing must wait if there is a dependency on a register
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_ACC (cpu, in_ACC40Si);
  post_wait_for_ACC (cpu, ACC40Si_1);
  post_wait_for_ACC (cpu, out_ACC40Sk);

  /* Restore the busy cycles of the registers we used.  */
  acc = ps->acc_busy;
  acc[in_ACC40Si] += busy_adjustment[0];
  if (ACC40Si_1 >= 0)
    acc[ACC40Si_1] += busy_adjustment[1];
  acc[out_ACC40Sk] += busy_adjustment[2];

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
  set_acc_use_is_media_p2 (cpu, out_ACC40Sk);

  return cycles;
}

int
frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
				      int unit_num, int referenced,
				      INT in_ACC40Si, INT out_ACC40Sk)
{
  int cycles;
  INT ACC40Si_1;
  INT ACC40Si_2;
  INT ACC40Si_3;
  INT ACC40Sk_1;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
  int *acc;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ACC40Si_1 = DUAL_REG (in_ACC40Si);
  ACC40Si_2 = DUAL_REG (ACC40Si_1);
  ACC40Si_3 = DUAL_REG (ACC40Si_2);
  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);

  ps = CPU_PROFILE_STATE (cpu);
  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 13-8 in the LSI.  */
  if (acc_use_is_media_p2 (cpu, in_ACC40Si))
    {
      busy_adjustment[0] = 1;
      decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]);
    }
  if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1))
    {
      busy_adjustment[1] = 1;
      decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]);
    }
  if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2))
    {
      busy_adjustment[2] = 1;
      decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]);
    }
  if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3))
    {
      busy_adjustment[3] = 1;
      decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]);
    }
  if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1
      && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3)
    {
      if (acc_use_is_media_p2 (cpu, out_ACC40Sk))
	{
	  busy_adjustment[4] = 1;
	  decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
	}
    }
  if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1
      && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3)
    {
      if (acc_use_is_media_p2 (cpu, ACC40Sk_1))
	{
	  busy_adjustment[5] = 1;
	  decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
	}
    }

  /* The post processing must wait if there is a dependency on a register
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_ACC (cpu, in_ACC40Si);
  post_wait_for_ACC (cpu, ACC40Si_1);
  post_wait_for_ACC (cpu, ACC40Si_2);
  post_wait_for_ACC (cpu, ACC40Si_3);
  post_wait_for_ACC (cpu, out_ACC40Sk);
  post_wait_for_ACC (cpu, ACC40Sk_1);

  /* Restore the busy cycles of the registers we used.  */
  acc = ps->acc_busy;
  acc[in_ACC40Si] += busy_adjustment[0];
  if (ACC40Si_1 >= 0)
    acc[ACC40Si_1] += busy_adjustment[1];
  if (ACC40Si_2 >= 0)
    acc[ACC40Si_2] += busy_adjustment[2];
  if (ACC40Si_3 >= 0)
    acc[ACC40Si_3] += busy_adjustment[3];
  acc[out_ACC40Sk] += busy_adjustment[4];
  if (ACC40Sk_1 >= 0)
    acc[ACC40Sk_1] += busy_adjustment[5];

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
  set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
  if (ACC40Sk_1 >= 0)
    {
      update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
      set_acc_use_is_media_p2 (cpu, ACC40Sk_1);
    }

  return cycles;
}

int
frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
				     int unit_num, int referenced,
				     INT in_ACC40Si, INT out_ACC40Sk)
{
  int cycles;
  INT ACC40Si_1;
  INT ACC40Sk_1;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0, 0, 0, 0};
  int *acc;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ACC40Si_1 = DUAL_REG (in_ACC40Si);
  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);

  ps = CPU_PROFILE_STATE (cpu);
  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 13-8 in the LSI.  */
  if (acc_use_is_media_p2 (cpu, in_ACC40Si))
    {
      busy_adjustment[0] = 1;
      decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]);
    }
  if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1))
    {
      busy_adjustment[1] = 1;
      decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]);
    }
  if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1)
    {
      if (acc_use_is_media_p2 (cpu, out_ACC40Sk))
	{
	  busy_adjustment[2] = 1;
	  decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
	}
    }
  if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1)
    {
      if (acc_use_is_media_p2 (cpu, ACC40Sk_1))
	{
	  busy_adjustment[3] = 1;
	  decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[3]);
	}
    }

  /* The post processing must wait if there is a dependency on a register
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_ACC (cpu, in_ACC40Si);
  post_wait_for_ACC (cpu, ACC40Si_1);
  post_wait_for_ACC (cpu, out_ACC40Sk);
  post_wait_for_ACC (cpu, ACC40Sk_1);

  /* Restore the busy cycles of the registers we used.  */
  acc = ps->acc_busy;
  acc[in_ACC40Si] += busy_adjustment[0];
  if (ACC40Si_1 >= 0)
    acc[ACC40Si_1] += busy_adjustment[1];
  acc[out_ACC40Sk] += busy_adjustment[2];
  if (ACC40Sk_1 >= 0)
    acc[ACC40Sk_1] += busy_adjustment[3];

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
  set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
  if (ACC40Sk_1 >= 0)
    {
      update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
      set_acc_use_is_media_p2 (cpu, ACC40Sk_1);
    }

  return cycles;
}

int
frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
					  int unit_num, int referenced,
					  INT in_ACC40Si, INT out_ACC40Sk)
{
  int cycles;
  INT ACC40Si_1;
  INT ACC40Si_2;
  INT ACC40Si_3;
  INT ACC40Sk_1;
  INT ACC40Sk_2;
  INT ACC40Sk_3;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0, 0};
  int *acc;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ACC40Si_1 = DUAL_REG (in_ACC40Si);
  ACC40Si_2 = DUAL_REG (ACC40Si_1);
  ACC40Si_3 = DUAL_REG (ACC40Si_2);
  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
  ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
  ACC40Sk_3 = DUAL_REG (ACC40Sk_2);

  ps = CPU_PROFILE_STATE (cpu);
  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 13-8 in the LSI.  */
  if (acc_use_is_media_p2 (cpu, in_ACC40Si))
    {
      busy_adjustment[0] = 1;
      decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]);
    }
  if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1))
    {
      busy_adjustment[1] = 1;
      decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]);
    }
  if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2))
    {
      busy_adjustment[2] = 1;
      decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]);
    }
  if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3))
    {
      busy_adjustment[3] = 1;
      decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]);
    }
  if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1
      && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3)
    {
      if (acc_use_is_media_p2 (cpu, out_ACC40Sk))
	{
	  busy_adjustment[4] = 1;
	  decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
	}
    }
  if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1
      && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3)
    {
      if (acc_use_is_media_p2 (cpu, ACC40Sk_1))
	{
	  busy_adjustment[5] = 1;
	  decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
	}
    }
  if (ACC40Sk_2 != in_ACC40Si && ACC40Sk_2 != ACC40Si_1
      && ACC40Sk_2 != ACC40Si_2 && ACC40Sk_2 != ACC40Si_3)
    {
      if (acc_use_is_media_p2 (cpu, ACC40Sk_2))
	{
	  busy_adjustment[6] = 1;
	  decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]);
	}
    }
  if (ACC40Sk_3 != in_ACC40Si && ACC40Sk_3 != ACC40Si_1
      && ACC40Sk_3 != ACC40Si_2 && ACC40Sk_3 != ACC40Si_3)
    {
      if (acc_use_is_media_p2 (cpu, ACC40Sk_3))
	{
	  busy_adjustment[7] = 1;
	  decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]);
	}
    }

  /* The post processing must wait if there is a dependency on a register
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_ACC (cpu, in_ACC40Si);
  post_wait_for_ACC (cpu, ACC40Si_1);
  post_wait_for_ACC (cpu, ACC40Si_2);
  post_wait_for_ACC (cpu, ACC40Si_3);
  post_wait_for_ACC (cpu, out_ACC40Sk);
  post_wait_for_ACC (cpu, ACC40Sk_1);
  post_wait_for_ACC (cpu, ACC40Sk_2);
  post_wait_for_ACC (cpu, ACC40Sk_3);

  /* Restore the busy cycles of the registers we used.  */
  acc = ps->acc_busy;
  acc[in_ACC40Si] += busy_adjustment[0];
  if (ACC40Si_1 >= 0)
    acc[ACC40Si_1] += busy_adjustment[1];
  if (ACC40Si_2 >= 0)
    acc[ACC40Si_2] += busy_adjustment[2];
  if (ACC40Si_3 >= 0)
    acc[ACC40Si_3] += busy_adjustment[3];
  acc[out_ACC40Sk] += busy_adjustment[4];
  if (ACC40Sk_1 >= 0)
    acc[ACC40Sk_1] += busy_adjustment[5];
  if (ACC40Sk_2 >= 0)
    acc[ACC40Sk_2] += busy_adjustment[6];
  if (ACC40Sk_3 >= 0)
    acc[ACC40Sk_3] += busy_adjustment[7];

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
  set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
  if (ACC40Sk_1 >= 0)
    {
      update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
      set_acc_use_is_media_p2 (cpu, ACC40Sk_1);
    }
  if (ACC40Sk_2 >= 0)
    {
      update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
      set_acc_use_is_media_p2 (cpu, ACC40Sk_2);
    }
  if (ACC40Sk_3 >= 0)
    {
      update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
      set_acc_use_is_media_p2 (cpu, ACC40Sk_3);
    }

  return cycles;
}

int
frvbf_model_fr400_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
			     int unit_num, int referenced,
			     INT in_FRi, INT in_FRj,
			     INT out_FRk)
{
  /* Modelling is the same as media unit 1.  */
  return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced,
				      in_FRi, in_FRj, out_FRk);
}

int
frvbf_model_fr400_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
				  int unit_num, int referenced,
				  INT in_FRi, INT out_FRk)