📄 profile-fr450.c
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intfrvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRi, INT in_FRj, INT out_ACC40Sk, INT out_ACC40Uk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced, in_FRi, in_FRj, out_ACC40Sk, out_ACC40Uk);}intfrvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRi, INT in_FRj, INT out_ACC40Sk, INT out_ACC40Uk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced, in_FRi, in_FRj, out_ACC40Sk, out_ACC40Uk);}intfrvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_ACC40Si, INT out_ACC40Sk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced, in_ACC40Si, out_ACC40Sk);}intfrvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_ACC40Si, INT out_ACC40Sk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num, referenced, in_ACC40Si, out_ACC40Sk);}intfrvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_ACC40Si, INT out_ACC40Sk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num, referenced, in_ACC40Si, out_ACC40Sk);}intfrvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_ACC40Si, INT out_ACC40Sk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num, referenced, in_ACC40Si, out_ACC40Sk);}intfrvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRi, INT in_FRj, INT out_FRk){ /* Modelling is the same as media unit 1. */ return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced, in_FRi, in_FRj, out_FRk);}intfrvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRi, INT out_FRk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced, in_FRi, out_FRk);}intfrvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRi, INT in_FRj, INT out_FRk){ /* Modelling is the same as media unit 1. */ return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced, in_FRi, in_FRj, out_FRk);}intfrvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_ACC40Si, INT in_FRj, INT out_ACC40Sk, INT out_FRk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, in_ACC40Si, in_FRj, out_ACC40Sk, out_FRk);}intfrvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_ACCGi, INT in_FRinti, INT out_ACCGk, INT out_FRintk){ /* Modelling is the same as media-4 unit except use accumulator guards as input instead of accumulators. */ return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);}intfrvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_ACC40Si, INT out_FRk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num, referenced, in_ACC40Si, out_FRk);}intfrvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced){ int cycles; int acc; FRV_PROFILE_STATE *ps; if (model_insn == FRV_INSN_MODEL_PASS_1) return 0; /* The preprocessing can execute right away. */ cycles = idesc->timing->units[unit_num].done; ps = CPU_PROFILE_STATE (cpu); /* The post processing must wait for any pending ACC writes. */ ps->post_wait = cycles; for (acc = 0; acc < 4; acc++) post_wait_for_ACC (cpu, acc); for (acc = 8; acc < 12; acc++) post_wait_for_ACC (cpu, acc); for (acc = 0; acc < 4; acc++) { update_ACC_latency (cpu, acc, ps->post_wait); update_ACC_ptime (cpu, acc, 2); } for (acc = 8; acc < 12; acc++) { update_ACC_latency (cpu, acc, ps->post_wait); update_ACC_ptime (cpu, acc, 2); } return cycles;}intfrvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRi, INT out_FRk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced, in_FRi, out_FRk);}intfrvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRinti, INT in_FRintj, INT out_FCCk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced, in_FRinti, in_FRintj, out_FCCk);}intfrvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRi, INT out_FRk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num, referenced, in_FRi, out_FRk);}intfrvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_FRj, INT out_FRk){ /* Modelling for this unit is the same as for fr400. */ return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num, referenced, in_FRj, out_FRk);}intfrvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_GRi, INT in_GRj){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, in_GRi, in_GRj);}intfrvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_GRi, INT in_GRj){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, in_GRi, in_GRj);}intfrvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_GRi, INT in_GRj){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, in_GRi, in_GRj);}intfrvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_GRi, INT in_GRj){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, in_GRi, in_GRj);}intfrvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_GRi, INT in_GRj){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, in_GRi, in_GRj);}intfrvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_GRi, INT in_GRj){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, in_GRi, in_GRj);}intfrvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT in_GRi, INT in_GRj){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, in_GRi, in_GRj);}intfrvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);}intfrvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced){ /* Modelling for this unit is the same as for fr500. */ return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);}#endif /* WITH_PROFILE_MODEL_P */
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