profile.c

这个是LINUX下的GDB调度工具的源码

    }
}

/* Top up the latency of the given double GR by the number of cycles.  */
void
update_GRdouble_latency (SIM_CPU *cpu, INT out_GR, int cycles)
{
  if (out_GR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *gr = ps->gr_latency;
      if (gr[out_GR] < cycles)
	gr[out_GR] = cycles;
      if (out_GR < 63 && gr[out_GR + 1] < cycles)
	gr[out_GR + 1] = cycles;
    }
}

void
update_GR_latency_for_load (SIM_CPU *cpu, INT out_GR, int cycles)
{
  if (out_GR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *gr = ps->gr_latency;

      /* The latency of the GR will be at least the number of cycles used
	 by the insn.  */
      if (gr[out_GR] < cycles)
	gr[out_GR] = cycles;

      /* The latency will also depend on how long it takes to retrieve the
	 data from the cache or memory.  Assume that the load is issued
	 after the last cycle of the insn.  */
      request_cache_load (cpu, out_GR, REGTYPE_NONE, cycles);
    }
}

void
update_GRdouble_latency_for_load (SIM_CPU *cpu, INT out_GR, int cycles)
{
  if (out_GR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *gr = ps->gr_latency;

      /* The latency of the GR will be at least the number of cycles used
	 by the insn.  */
      if (gr[out_GR] < cycles)
	gr[out_GR] = cycles;
      if (out_GR < 63 && gr[out_GR + 1] < cycles)
	gr[out_GR + 1] = cycles;

      /* The latency will also depend on how long it takes to retrieve the
	 data from the cache or memory.  Assume that the load is issued
	 after the last cycle of the insn.  */
      request_cache_load (cpu, out_GR, REGTYPE_NONE, cycles);
    }
}

void
update_GR_latency_for_swap (SIM_CPU *cpu, INT out_GR, int cycles)
{
  update_GR_latency_for_load (cpu, out_GR, cycles);
}

/* Top up the latency of the given FR by the given number of cycles.  */
void
update_FR_latency (SIM_CPU *cpu, INT out_FR, int cycles)
{
  if (out_FR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *fr = ps->fr_latency;
      if (fr[out_FR] < cycles)
	fr[out_FR] = cycles;
    }
}

/* Top up the latency of the given double FR by the number of cycles.  */
void
update_FRdouble_latency (SIM_CPU *cpu, INT out_FR, int cycles)
{
  if (out_FR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *fr = ps->fr_latency;
      if (fr[out_FR] < cycles)
	fr[out_FR] = cycles;
      if (out_FR < 63 && fr[out_FR + 1] < cycles)
	fr[out_FR + 1] = cycles;
    }
}

void
update_FR_latency_for_load (SIM_CPU *cpu, INT out_FR, int cycles)
{
  if (out_FR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *fr = ps->fr_latency;

      /* The latency of the FR will be at least the number of cycles used
	 by the insn.  */
      if (fr[out_FR] < cycles)
	fr[out_FR] = cycles;

      /* The latency will also depend on how long it takes to retrieve the
	 data from the cache or memory.  Assume that the load is issued
	 after the last cycle of the insn.  */
      request_cache_load (cpu, out_FR, REGTYPE_FR, cycles);
    }
}

void
update_FRdouble_latency_for_load (SIM_CPU *cpu, INT out_FR, int cycles)
{
  if (out_FR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *fr = ps->fr_latency;
	  
      /* The latency of the FR will be at least the number of cycles used
	 by the insn.  */
      if (fr[out_FR] < cycles)
	fr[out_FR] = cycles;
      if (out_FR < 63 && fr[out_FR + 1] < cycles)
	fr[out_FR + 1] = cycles;

      /* The latency will also depend on how long it takes to retrieve the
	 data from the cache or memory.  Assume that the load is issued
	 after the last cycle of the insn.  */
      request_cache_load (cpu, out_FR, REGTYPE_FR, cycles);
    }
}

/* Top up the post-processing time of the given FR by the given number of
   cycles.  */
void
update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
{
  if (out_FR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      /* If a load is pending on this register, then add the cycles to
	 the post processing time for this register. Otherwise apply it
	 directly to the latency of the register.  */
      if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
	{
	  int *fr = ps->fr_latency;
	  fr[out_FR] += cycles;
	}
      else
	ps->fr_ptime[out_FR] += cycles;
    }
}

void
update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
{
  if (out_FR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      /* If a load is pending on this register, then add the cycles to
	 the post processing time for this register. Otherwise apply it
	 directly to the latency of the register.  */
      if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
	{
	  int *fr = ps->fr_latency;
	  fr[out_FR] += cycles;
	  if (out_FR < 63)
	    fr[out_FR + 1] += cycles;
	}
      else
	{
	  ps->fr_ptime[out_FR] += cycles;
	  if (out_FR < 63)
	    ps->fr_ptime[out_FR + 1] += cycles;
	}
    }
}

/* Top up the post-processing time of the given ACC by the given number of
   cycles.  */
void
update_ACC_ptime (SIM_CPU *cpu, INT out_ACC, int cycles)
{
  if (out_ACC >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      /* No load can be pending on this register. Apply the cycles
	 directly to the latency of the register.  */
      int *acc = ps->acc_latency;
      acc[out_ACC] += cycles;
    }
}

/* Top up the post-processing time of the given SPR by the given number of
   cycles.  */
void
update_SPR_ptime (SIM_CPU *cpu, INT out_SPR, int cycles)
{
  if (out_SPR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      /* No load can be pending on this register. Apply the cycles
	 directly to the latency of the register.  */
      int *spr = ps->spr_latency;
      spr[out_SPR] += cycles;
    }
}

void
decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
{
  if (out_ACC >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *acc = ps->acc_busy;
      acc[out_ACC] -= cycles;
      if (ps->acc_busy_adjust[out_ACC] >= 0
	  && cycles > ps->acc_busy_adjust[out_ACC])
	ps->acc_busy_adjust[out_ACC] = cycles;
    }
}

void
increase_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
{
  if (out_ACC >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *acc = ps->acc_busy;
      acc[out_ACC] += cycles;
    }
}

void
enforce_full_acc_latency (SIM_CPU *cpu, INT in_ACC)
{
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  ps->acc_busy_adjust [in_ACC] = -1;
}

void
decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
{
  if (out_FR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *fr = ps->fr_busy;
      fr[out_FR] -= cycles;
      if (ps->fr_busy_adjust[out_FR] >= 0
	  && cycles > ps->fr_busy_adjust[out_FR])
	ps->fr_busy_adjust[out_FR] = cycles;
    }
}

void
increase_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
{
  if (out_FR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *fr = ps->fr_busy;
      fr[out_FR] += cycles;
    }
}

/* Top up the latency of the given ACC by the given number of cycles.  */
void
update_ACC_latency (SIM_CPU *cpu, INT out_ACC, int cycles)
{
  if (out_ACC >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *acc = ps->acc_latency;
      if (acc[out_ACC] < cycles)
	acc[out_ACC] = cycles;
    }
}

/* Top up the latency of the given CCR by the given number of cycles.  */
void
update_CCR_latency (SIM_CPU *cpu, INT out_CCR, int cycles)
{
  if (out_CCR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *ccr = ps->ccr_latency;
      if (ccr[out_CCR] < cycles)
	ccr[out_CCR] = cycles;
    }
}

/* Top up the latency of the given SPR by the given number of cycles.  */
void
update_SPR_latency (SIM_CPU *cpu, INT out_SPR, int cycles)
{
  if (out_SPR >= 0)
    {
      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
      int *spr = ps->spr_latency;
      if (spr[out_SPR] < cycles)
	spr[out_SPR] = cycles;
    }
}

/* Top up the latency of the given integer division resource by the given
   number of cycles.  */
void
update_idiv_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
{
  /* operate directly on the busy cycles since each resource can only
     be used once in a VLIW insn.  */
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *r = ps->idiv_busy;
  r[in_resource] = cycles;
}

/* Set the latency of the given resource to the given number of cycles.  */
void
update_fdiv_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
{
  /* operate directly on the busy cycles since each resource can only
     be used once in a VLIW insn.  */
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *r = ps->fdiv_busy;
  r[in_resource] = cycles;
}

/* Set the latency of the given resource to the given number of cycles.  */
void
update_fsqrt_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
{
  /* operate directly on the busy cycles since each resource can only
     be used once in a VLIW insn.  */
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *r = ps->fsqrt_busy;
  r[in_resource] = cycles;
}

/* Set the latency of the given resource to the given number of cycles.  */
void
update_float_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
{
  /* operate directly on the busy cycles since each resource can only
     be used once in a VLIW insn.  */
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *r = ps->float_busy;
  r[in_resource] = cycles;
}

void
update_media_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
{
  /* operate directly on the busy cycles since each resource can only
     be used once in a VLIW insn.  */
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *r = ps->media_busy;
  r[in_resource] = cycles;
}

/* Set the branch penalty to the given number of cycles.  */
void
update_branch_penalty (SIM_CPU *cpu, int cycles)
{
  /* operate directly on the busy cycles since only one branch can occur
     in a VLIW insn.  */
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  ps->branch_penalty = cycles;
}

/* Check the availability of the given GR register and update the number
   of cycles the current VLIW insn must wait until it is available.  */
void
vliw_wait_for_GR (SIM_CPU *cpu, INT in_GR)
{
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *gr = ps->gr_busy;
  /* If the latency of the register is greater than the current wait
     then update the current wait.  */
  if (in_GR >= 0 && gr[in_GR] > ps->vliw_wait)
    {
      if (TRACE_INSN_P (cpu))
	sprintf (hazard_name, "Data hazard for gr%d:", in_GR);
      ps->vliw_wait = gr[in_GR];
    }
}

/* Check the availability of the given GR register and update the number
   of cycles the current VLIW insn must wait until it is available.  */
void
vliw_wait_for_GRdouble (SIM_CPU *cpu, INT in_GR)
{
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *gr = ps->gr_busy;
  /* If the latency of the register is greater than the current wait
     then update the current wait.  */
  if (in_GR >= 0)
    {
      if (gr[in_GR] > ps->vliw_wait)
	{
	  if (TRACE_INSN_P (cpu))
	    sprintf (hazard_name, "Data hazard for gr%d:", in_GR);
	  ps->vliw_wait = gr[in_GR];
	}
      if (in_GR < 63 && gr[in_GR + 1] > ps->vliw_wait)
	{
	  if (TRACE_INSN_P (cpu))
	    sprintf (hazard_name, "Data hazard for gr%d:", in_GR + 1);
	  ps->vliw_wait = gr[in_GR + 1];
	}
    }
}

/* Check the availability of the given FR register and update the number
   of cycles the current VLIW insn must wait until it is available.  */
void
vliw_wait_for_FR (SIM_CPU *cpu, INT in_FR)
{
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *fr = ps->fr_busy;
  /* If the latency of the register is greater than the current wait
     then update the current wait.  */
  if (in_FR >= 0 && fr[in_FR] > ps->vliw_wait)
    {
      if (TRACE_INSN_P (cpu))
	sprintf (hazard_name, "Data hazard for fr%d:", in_FR);
      ps->vliw_wait = fr[in_FR];
    }
}

/* Check the availability of the given GR register and update the number
   of cycles the current VLIW insn must wait until it is available.  */
void
vliw_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR)
{
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *fr = ps->fr_busy;
  /* If the latency of the register is greater than the current wait
     then update the current wait.  */
  if (in_FR >= 0)
    {
      if (fr[in_FR] > ps->vliw_wait)
	{
	  if (TRACE_INSN_P (cpu))
	    sprintf (hazard_name, "Data hazard for fr%d:", in_FR);
	  ps->vliw_wait = fr[in_FR];
	}
      if (in_FR < 63 && fr[in_FR + 1] > ps->vliw_wait)
	{
	  if (TRACE_INSN_P (cpu))
	    sprintf (hazard_name, "Data hazard for fr%d:", in_FR + 1);
	  ps->vliw_wait = fr[in_FR + 1];
	}
    }
}

/* Check the availability of the given CCR register and update the number
   of cycles the current VLIW insn must wait until it is available.  */
void
vliw_wait_for_CCR (SIM_CPU *cpu, INT in_CCR)
{
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *ccr = ps->ccr_busy;
  /* If the latency of the register is greater than the current wait
     then update the current wait.  */
  if (in_CCR >= 0 && ccr[in_CCR] > ps->vliw_wait)
    {
      if (TRACE_INSN_P (cpu))
	{
	  if (in_CCR > 3)
	    sprintf (hazard_name, "Data hazard for icc%d:", in_CCR-4);
	  else
	    sprintf (hazard_name, "Data hazard for fcc%d:", in_CCR);
	}
      ps->vliw_wait = ccr[in_CCR];
    }
}

/* Check the availability of the given ACC register and update the number
   of cycles the current VLIW insn must wait until it is available.  */
void
vliw_wait_for_ACC (SIM_CPU *cpu, INT in_ACC)
{
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *acc = ps->acc_busy;
  /* If the latency of the register is greater than the current wait
     then update the current wait.  */
  if (in_ACC >= 0 && acc[in_ACC] > ps->vliw_wait)
    {
      if (TRACE_INSN_P (cpu))
	sprintf (hazard_name, "Data hazard for acc%d:", in_ACC);
      ps->vliw_wait = acc[in_ACC];
    }
}

/* Check the availability of the given SPR register and update the number
   of cycles the current VLIW insn must wait until it is available.  */
void
vliw_wait_for_SPR (SIM_CPU *cpu, INT in_SPR)
{
  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
  int *spr = ps->spr_busy;
  /* If the latency of the register is greater than the current wait
     then update the current wait.  */
  if (in_SPR >= 0 && spr[in_SPR] > ps->vliw_wait)
    {
      if (TRACE_INSN_P (cpu))
	sprintf (hazard_name, "Data hazard for spr %d:", in_SPR);
      ps->vliw_wait = spr[in_SPR];
    }
}

/* Check the availability of the given integer division resource and update
   the number of cycles the current VLIW insn must wait until it is available.
*/
void
vliw_wait_for_idiv_resource (SIM_CPU *cpu, INT in_resource)
{