profile-fr500.c

这个是LINUX下的GDB调度工具的源码

{
  int cycles;
  FRV_VLIW *vliw;
  int slot;
  INT dual_FRj;
  INT dual_FRk;
  FRV_PROFILE_STATE *ps;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  cycles = idesc->timing->units[unit_num].done;

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  dual_FRj = DUAL_REG (in_FRj);
  dual_FRk = DUAL_REG (out_FRk);
  adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
  adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_FR (cpu, dual_FRj);
  post_wait_for_FR (cpu, dual_FRk);

  vliw = CPU_VLIW (cpu);
  slot = vliw->next_slot - 1;
  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
  post_wait_for_fsqrt (cpu, slot);
  restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
  restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);

  /* The latency of FRk will be at least the latency of the other inputs.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_latency (cpu, dual_FRk, ps->post_wait);

  /* Once initiated, post-processing will take 15 cycles.  */
  update_FR_ptime (cpu, out_FRk, 15);
  update_FR_ptime (cpu, dual_FRk, 15);

  /* The latency of the sqrt unit will be at least the latency of the other
     inputs.  */
  update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);

  /* Mark this use of the register as a floating point op.  */
  if (out_FRk >= 0)
    set_use_is_fpop (cpu, out_FRk);
  if (dual_FRk >= 0)
    set_use_is_fpop (cpu, dual_FRk);

  return cycles;
}

int
frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc,
				   int unit_num, int referenced,
				   INT in_FRi, INT in_FRj,
				   INT in_FRdoublei, INT in_FRdoublej,
				   INT out_FCCi_2)
{
  int cycles;
  FRV_PROFILE_STATE *ps;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FRdouble (cpu, in_FRdoublei);
  post_wait_for_FRdouble (cpu, in_FRdoublej);
  post_wait_for_CCR (cpu, out_FCCi_2);
  restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);

  /* The latency of FCCi_2 will be the latency of the other inputs plus 3
     cycles.  */
  update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);

  return cycles;
}

int
frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc,
					int unit_num, int referenced,
					INT in_FRi, INT in_FRj,
					INT out_FCCi_2)
{
  int cycles;
  INT dual_FRi;
  INT dual_FRj;
  INT dual_FCCi_2;
  FRV_PROFILE_STATE *ps;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  dual_FRi = DUAL_REG (in_FRi);
  dual_FRj = DUAL_REG (in_FRj);
  dual_FCCi_2 = out_FCCi_2 + 1;
  adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
  adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, dual_FRi);
  post_wait_for_FR (cpu, dual_FRj);
  post_wait_for_CCR (cpu, out_FCCi_2);
  post_wait_for_CCR (cpu, dual_FCCi_2);
  restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
  restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);

  /* The latency of FCCi_2 will be the latency of the other inputs plus 3
     cycles.  */
  update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
  update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3);

  return cycles;
}

int
frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc,
				   int unit_num, int referenced,
				   INT in_FRj, INT in_FRintj, INT in_FRdoublej,
				   INT out_FRk, INT out_FRintk,
				   INT out_FRdoublek)
{
  int cycles;
  FRV_PROFILE_STATE *ps;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
  adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
  adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, in_FRintj);
  post_wait_for_FRdouble (cpu, in_FRdoublej);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_FR (cpu, out_FRintk);
  post_wait_for_FRdouble (cpu, out_FRdoublek);
  if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
    {
      post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
      post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk));
      post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
    }
  restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
  restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
  restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);

  /* The latency of FRk will be at least the latency of the other inputs.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_latency (cpu, out_FRintk, ps->post_wait);
  update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);

  if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
    {
      update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
      update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait);
      update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
    }

  /* Once initiated, post-processing will take 3 cycles.  */
  update_FR_ptime (cpu, out_FRk, 3);
  update_FR_ptime (cpu, out_FRintk, 3);
  update_FRdouble_ptime (cpu, out_FRdoublek, 3);

  if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
    {
      update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
      update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 3);
      update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
    }

  /* Mark this use of the register as a floating point op.  */
  if (out_FRk >= 0)
    set_use_is_fpop (cpu, out_FRk);
  if (out_FRintk >= 0)
    set_use_is_fpop (cpu, out_FRintk);
  if (out_FRdoublek >= 0)
    {
      set_use_is_fpop (cpu, out_FRdoublek);
      set_use_is_fpop (cpu, out_FRdoublek + 1);
    }

  return cycles;
}

int
frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc,
					int unit_num, int referenced,
					INT in_FRj, INT in_FRintj,
					INT out_FRk, INT out_FRintk)
{
  int cycles;
  INT dual_FRj;
  INT dual_FRintj;
  INT dual_FRk;
  INT dual_FRintk;
  FRV_PROFILE_STATE *ps;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  dual_FRj = DUAL_REG (in_FRj);
  dual_FRintj = DUAL_REG (in_FRintj);
  dual_FRk = DUAL_REG (out_FRk);
  dual_FRintk = DUAL_REG (out_FRintk);
  adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
  adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
  adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
  adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, in_FRintj);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_FR (cpu, out_FRintk);
  post_wait_for_FR (cpu, dual_FRj);
  post_wait_for_FR (cpu, dual_FRintj);
  post_wait_for_FR (cpu, dual_FRk);
  post_wait_for_FR (cpu, dual_FRintk);
  restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
  restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
  restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
  restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);

  /* The latency of FRk will be at least the latency of the other inputs.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_latency (cpu, out_FRintk, ps->post_wait);
  update_FR_latency (cpu, dual_FRk, ps->post_wait);
  update_FR_latency (cpu, dual_FRintk, ps->post_wait);

  /* Once initiated, post-processing will take 3 cycles.  */
  update_FR_ptime (cpu, out_FRk, 3);
  update_FR_ptime (cpu, out_FRintk, 3);
  update_FR_ptime (cpu, dual_FRk, 3);
  update_FR_ptime (cpu, dual_FRintk, 3);

  /* Mark this use of the register as a floating point op.  */
  if (out_FRk >= 0)
    set_use_is_fpop (cpu, out_FRk);
  if (out_FRintk >= 0)
    set_use_is_fpop (cpu, out_FRintk);

  return cycles;
}

int
frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
			   int unit_num, int referenced,
			   INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi,
			   INT out_FRk,
			   INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  const CGEN_INSN *insn;
  int is_media_s1;
  int is_media_s2;
  int busy_adjustment[] = {0, 0, 0};
  int *fr;
  int *acc;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ps = CPU_PROFILE_STATE (cpu);
  insn = idesc->idata;

  /* If the previous use of the registers was a media op,
     then their latency will be less than previously recorded.
     See Table 13-13 in the LSI.  */
  if (in_FRi >= 0)
    {
      if (use_is_media (cpu, in_FRi))
	{
	  busy_adjustment[0] = 2;
	  decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
	}
      else
	enforce_full_fr_latency (cpu, in_FRi);
    }
  if (in_FRj >= 0 && in_FRj != in_FRi)
    {
      if (use_is_media (cpu, in_FRj))
	{
	  busy_adjustment[1] = 2;
	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
	}
      else
	enforce_full_fr_latency (cpu, in_FRj);
    }
  if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
    {
      if (use_is_media (cpu, out_FRk))
	{
	  busy_adjustment[2] = 2;
	  decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
	}
      else
	enforce_full_fr_latency (cpu, out_FRk);
    }

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_ACC (cpu, in_ACC40Si);
  post_wait_for_ACC (cpu, in_ACCGi);
  post_wait_for_ACC (cpu, out_ACC40Sk);
  post_wait_for_ACC (cpu, out_ACC40Uk);
  post_wait_for_ACC (cpu, out_ACCGk);

  /* Restore the busy cycles of the registers we used.  */
  fr = ps->fr_busy;
  if (in_FRi >= 0)
    fr[in_FRi] += busy_adjustment[0];
  if (in_FRj >= 0)
    fr[in_FRj] += busy_adjustment[1];
  if (out_FRk >= 0)
    fr[out_FRk] += busy_adjustment[2];

  /* The latency of tht output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 3 cycles.  */
  if (out_FRk >= 0)
    {
      update_FR_latency (cpu, out_FRk, ps->post_wait);
      update_FR_ptime (cpu, out_FRk, 3);
      /* Mark this use of the register as a media op.  */
      set_use_is_media (cpu, out_FRk);
    }
  /* The latency of tht output accumulator will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  if (out_ACC40Sk >= 0)
    update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
  if (out_ACC40Uk >= 0)
    update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
  if (out_ACCGk >= 0)
    update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1);

  return cycles;
}

int
frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc,
				       int unit_num, int referenced,
				       INT in_FRi, INT in_FRj,
				       INT out_FRk)
{
  int cycles;
  INT dual_FRi;
  INT dual_FRj;
  INT dual_FRk;
  FRV_PROFILE_STATE *ps;
  int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
  int *fr;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ps = CPU_PROFILE_STATE (cpu);
  dual_FRi = DUAL_REG (in_FRi);
  dual_FRj = DUAL_REG (in_FRj);
  dual_FRk = DUAL_REG (out_FRk);

  /* If the previous use of the registers was a media op,
     then their latency will be less than previously recorded.
     See Table 13-13 in the LSI.  */
  if (use_is_media (cpu, in_FRi))
    {
      busy_adjustment[0] = 2;
      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
    }
  else
    enforce_full_fr_latency (cpu, in_FRi);
  if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi))
    {
      busy_adjustment[1] = 2;
      decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
    }
  else
    enforce_full_fr_latency (cpu, dual_FRi);
  if (in_FRj != in_FRi)
    {
      if (use_is_media (cpu, in_FRj))
	{
	  busy_adjustment[2] = 2;
	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
	}
      else
	enforce_full_fr_latency (cpu, in_FRj);
      if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj))
	{
	  busy_adjustment[3] = 2;
	  decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]);
	}
      else
	enforce_full_fr_latency (cpu, dual_FRj + 1);
    }
  if (out_FRk != in_FRi && out_FRk != in_FRj)
    {
      if (