frv-sim.h

这个是LINUX下的GDB调度工具的源码

  (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
)

#define SET_ESR_REC(esr, rec) (                        \
  (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
)

#define SET_ESR_IAEC(esr, iaec) (                       \
  (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
)

#define SET_ESR_DAEC(esr, daec) (                       \
  (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
)

#define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
#define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))

#define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
#define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
#define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))

#define GET_ESR_EDN(esr) ( \
  ((esr) >> 13) & 0xf      \
)
#define SET_ESR_EDN(esr, edn) (                       \
  (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
)

#define SET_EPCR(index, address) \
  (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))

#define SET_EAR(index, address) \
  (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))

#define SET_EDR(index, edr) \
  (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))

#define GET_ESFR(index) \
  (CPU (h_spr[H_SPR_ESFR0 + (index)]))
#define SET_ESFR(index, esfr) \
  (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))

#define GET_ESFR_FLAG(findex) ( \
  (findex) > 31 ? \
    ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
    : \
    ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
)
#define SET_ESFR_FLAG(findex) ( \
  (findex) > 31 ? \
    (CPU (h_spr[H_SPR_ESFR0]) = \
      (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
    ) : \
    (CPU (h_spr[H_SPR_ESFR1]) = \
      (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
    ) \
)

/* The FSR registers.
   Get and set the hardware directly, since we may be getting/setting fields
   which are not accessible to the user.  */
#define GET_FSR(index) \
  (CPU (h_spr[H_SPR_FSR0 + (index)]))
#define SET_FSR(index, fsr) \
  (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))

#define GET_FSR_TEM(fsr) ( \
  ((fsr) >> 24) & 0x3f     \
)

#define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
#define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)

#define SET_FSR_FTT(fsr, ftt) (                          \
  (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
)

#define GET_FSR_AEXC(fsr) ( \
  ((fsr) >> 10) & 0x3f      \
)
#define SET_FSR_AEXC(fsr, aexc) (                          \
  (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
)

/* SIMD instruction exception codes for FQ.  */
enum frv_sie
{
  SIE_NIL   = 0,
  SIE_FRi   = 1,
  SIE_FRi_1 = 2
};

/* MIV field of FQ.  */
enum frv_miv
{
  MIV_FLOAT = 0,
  MIV_MEDIA = 1
};

/* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
   index here refers to the low order 32 bit element.
   Get and set the hardware directly, since we may be getting/setting fields
   which are not accessible to the user.  */
#define GET_FQ(index) \
  (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
#define SET_FQ(index, fq) \
  (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))

#define SET_FQ_MIV(fq, miv) (                          \
  (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
)

#define SET_FQ_SIE(fq, sie) (                          \
  (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
)

#define SET_FQ_FTT(fq, ftt) (                        \
  (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
)

#define SET_FQ_CEXC(fq, cexc) (                         \
  (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
)

#define GET_FQ_VALID(fq) ((fq) & 1)
#define SET_FQ_VALID(fq) ((fq) |= 1)

#define SET_FQ_OPC(index, insn) \
  (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))

/* mp_exception support.  */
/* Media trap types for MSR.  */
enum frv_msr_mtt
{
  MTT_NONE                = 0,
  MTT_OVERFLOW            = 1,
  MTT_ACC_NOT_ALIGNED     = 2,
  MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED.  */
  MTT_CR_NOT_ALIGNED      = 3,
  MTT_UNIMPLEMENTED_MPOP  = 5,
  MTT_INVALID_FR          = 6
};

/* Media status registers.
   Get and set the hardware directly, since we may be getting/setting fields
   which are not accessible to the user.  */
#define GET_MSR(index) \
  (CPU (h_spr[H_SPR_MSR0 + (index)]))
#define SET_MSR(index, msr) \
  (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))

#define GET_MSR_AOVF(msr) ((msr) & 1)
#define SET_MSR_AOVF(msr) ((msr) |=  1)

#define GET_MSR_OVF(msr) ( \
  ((msr) >> 1) & 0x1       \
)
#define SET_MSR_OVF(msr) ( \
  (msr) |= (1 << 1)        \
)
#define CLEAR_MSR_OVF(msr) ( \
  (msr) &= ~(1 << 1)         \
)

#define OR_MSR_SIE(msr, sie) (  \
  (msr) |= (((sie) & 0xf) << 2) \
)
#define CLEAR_MSR_SIE(msr) ( \
  (msr) &= ~(0xf << 2)       \
)

#define GET_MSR_MTT(msr) ( \
  ((msr) >> 12) & 0x7      \
)
#define SET_MSR_MTT(msr, mtt) (                          \
  (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
)
#define GET_MSR_EMCI(msr) ( \
  ((msr) >> 24) & 0x1       \
)
#define GET_MSR_MPEM(msr) ( \
  ((msr) >> 27) & 0x1        \
)
#define GET_MSR_SRDAV(msr) ( \
  ((msr) >> 28) & 0x1        \
)
#define GET_MSR_RDAV(msr) ( \
  ((msr) >> 29) & 0x1       \
)
#define GET_MSR_RD(msr) ( \
  ((msr) >> 30) & 0x3     \
)

void frvbf_media_register_not_aligned (SIM_CPU *);
void frvbf_media_acc_not_aligned (SIM_CPU *);
void frvbf_media_cr_not_aligned (SIM_CPU *);
void frvbf_media_overflow (SIM_CPU *, int);

/* Functions for queuing and processing interrupts.  */
struct frv_interrupt_queue_element *
frv_queue_break_interrupt (SIM_CPU *);

struct frv_interrupt_queue_element *
frv_queue_software_interrupt (SIM_CPU *, SI);

struct frv_interrupt_queue_element *
frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind);

struct frv_interrupt_queue_element *
frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);

struct frv_interrupt_queue_element *
frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);

struct frv_interrupt_queue_element *
frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);

struct frv_interrupt_queue_element *
frv_queue_float_disabled_interrupt (SIM_CPU *);

struct frv_interrupt_queue_element *
frv_queue_media_disabled_interrupt (SIM_CPU *);

struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);

struct frv_interrupt_queue_element *
frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec);

struct frv_interrupt_queue_element *
frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);

struct frv_interrupt_queue_element *
frv_queue_data_access_error_interrupt (SIM_CPU *, USI);

struct frv_interrupt_queue_element *
frv_queue_instruction_access_error_interrupt (SIM_CPU *);

struct frv_interrupt_queue_element *
frv_queue_instruction_access_exception_interrupt (SIM_CPU *);

struct frv_interrupt_queue_element *
frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);

enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);

struct frv_interrupt_queue_element *
frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);

void
frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *);

void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int);
void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *);

void frv_process_interrupts (SIM_CPU *);

void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR);
void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR);
void frv_program_interrupt (
  SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
);
void frv_software_interrupt (
  SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
);
void frv_external_interrupt (
  SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
);
void frv_program_or_software_interrupt (
  SIM_CPU *, struct frv_interrupt *, IADDR
);
void frv_clear_interrupt_classes (
  enum frv_interrupt_class, enum frv_interrupt_class
);

void
frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *);

/* Special purpose traps.  */
#define TRAP_SYSCALL	0x80
#define TRAP_BREAKPOINT	0x81
#define TRAP_REGDUMP1	0x82
#define TRAP_REGDUMP2	0x83

/* Handle the trap insns  */
void frv_itrap (SIM_CPU *, PCADDR, USI, int);
void frv_mtrap (SIM_CPU *);
/* Handle the break insn.  */
void frv_break (SIM_CPU *);
/* Handle the rett insn.  */
USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);

/* Parallel write queue flags.  */
#define FRV_WRITE_QUEUE_FORCE_WRITE 1

#define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)

/* Functions and macros for handling non-excepting instruction side effects.
   Get and set the hardware directly, since we may be getting/setting fields
   which are not accessible to the user.  */
#define GET_NECR()           (GET_H_SPR (H_SPR_NECR))
#define GET_NECR_ELOS(necr)  (((necr) >> 6) & 1)
#define GET_NECR_NEN(necr)   (((necr) >> 1) & 0x1f)
#define GET_NECR_VALID(necr) (((necr)     ) & 1)

#define NO_NESR    (-1)
/* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
   Architecture volume 1.  */
#define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
#define NESR_REGISTER_NOT_ALIGNED    0x1
#define NESR_UQI_SIZE 0
#define NESR_QI_SIZE  1
#define NESR_UHI_SIZE 2
#define NESR_HI_SIZE  3
#define NESR_SI_SIZE  4
#define NESR_DI_SIZE  5
#define NESR_XI_SIZE  6

#define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
#define SET_NESR(index, value) (                          \
  sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,    \
			 H_SPR_NESR0 + (index), (value)), \
  frvbf_force_update (current_cpu)                        \
)
#define GET_NESR_VALID(nesr) ((nesr) & 1)
#define SET_NESR_VALID(nesr) ((nesr) |= 1)

#define SET_NESR_EAV(nesr)   ((nesr) |= (1 << 31))

#define GET_NESR_FR(nesr)    (((nesr) >> 30) & 1)
#define SET_NESR_FR(nesr)    ((nesr) |= (1 << 30))
#define CLEAR_NESR_FR(nesr)  ((nesr) &= ~(1 << 30))

#define GET_NESR_DRN(nesr)   (((nesr) >> 24) & 0x3f)
#define SET_NESR_DRN(nesr, drn) (                            \
  (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
)

#define SET_NESR_SIZE(nesr, data_size) (                         \
  (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
)

#define SET_NESR_NEAN(nesr, index) (                           \
  (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
)

#define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
#define SET_NESR_DAEC(nesr, daec) (                   \
  (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
)

#define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
#define SET_NESR_REC(nesr, rec) (                    \
  (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
)

#define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
#define SET_NESR_EC(nesr, ec) (                       \
  (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
)

#define SET_NEEAR(index, address) ( \
  sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,       \
			 H_SPR_NEEAR0 + (index), (address)), \
  frvbf_force_update (current_cpu)                           \
)

#define GET_NE_FLAGS(flags, NE_base) (   \
  (flags)[0] = GET_H_SPR ((NE_base)),    \
  (flags)[1] = GET_H_SPR ((NE_base) + 1) \
)
#define SET_NE_FLAGS(NE_base, flags) ( \
  sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base),      \
                         (flags)[0]),                                  \
  frvbf_force_update (current_cpu),                                    \
  sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1,  \
                         (flags)[1]),                                  \
  frvbf_force_update (current_cpu)                                     \
)

#define GET_NE_FLAG(flags, index) (    \
  (index) > 31 ?                       \
    ((flags[0] >> ((index) - 32)) & 1) \
  :                                    \
    ((flags[1] >> (index)) & 1)        \
)
#define SET_NE_FLAG(flags, index) (       \
  (index) > 31 ?                          \
    ((flags)[0] |= (1 << ((index) - 32))) \
  :                                       \
    ((flags)[1] |= (1 << (index)))        \
)
#define CLEAR_NE_FLAG(flags, index) (      \
  (index) > 31 ?                           \
    ((flags)[0] &= ~(1 << ((index) - 32))) \
  :                                        \
    ((flags)[1] &= ~(1 << (index)))        \
)

BI   frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);

void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
void frvbf_commit (SIM_CPU *, SI, BI);

void frvbf_fpu_error (CGEN_FPU *, int);

void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *);

extern int insns_in_slot[];

#define COUNT_INSNS_IN_SLOT(slot) \
{                                 \
  if (WITH_PROFILE_MODEL_P)       \
    ++insns_in_slot[slot];        \
}
    
#define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
    
/* Multiple loads and stores.  */
void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);

/* Memory and cache support.  */
QI  frvbf_read_mem_QI  (SIM_CPU *, IADDR, SI);
UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI);
HI  frvbf_read_mem_HI  (SIM_CPU *, IADDR, SI);
UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI);
SI  frvbf_read_mem_SI  (SIM_CPU *, IADDR, SI);
SI  frvbf_read_mem_WI  (SIM_CPU *, IADDR, SI);
DI  frvbf_read_mem_DI  (SIM_CPU *, IADDR, SI);
DF  frvbf_read_mem_DF  (SIM_CPU *, IADDR, SI);

USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);

void frvbf_write_mem_QI  (SIM_CPU *, IADDR, SI, QI);
void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI);
void frvbf_write_mem_HI  (SIM_CPU *, IADDR, SI, HI);
void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI);
void frvbf_write_mem_SI  (SIM_CPU *, IADDR, SI, SI);
void frvbf_write_mem_WI  (SIM_CPU *, IADDR, SI, SI);
void frvbf_write_mem_DI  (SIM_CPU *, IADDR, SI, DI);
void frvbf_write_mem_DF  (SIM_CPU *, IADDR, SI, DF);

void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI);
void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI);
void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI);
void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI);
void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF);
void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);

void frv_set_write_queue_slot (SIM_CPU *current_cpu);

/* FRV specific options.  */
extern const OPTION frv_options[];

#endif /* FRV_SIM_H */