profile-fr550.c

这个是LINUX下的GDB调度工具的源码

  /* Restore the busy cycles of the registers we used.  */
  restore_float_register_busy_for_media (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1);

  /* The latency of tht output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  if (out_FRk >= 0)
    {
      update_FR_latency (cpu, out_FRk, ps->post_wait);
      update_FR_ptime (cpu, out_FRk, 1);
      /* Mark this use of the register as a media op.  */
      set_use_is_fr_complex_1 (cpu, out_FRk);
    }

  /* the floating point unit resource has a latency of 3 cycles  */
  update_float_resource_latency (cpu, slot, cycles + 3);

  return cycles;
}

int
frvbf_model_fr550_u_media_quad (SIM_CPU *cpu, const IDESC *idesc,
				int unit_num, int referenced,
				INT in_FRi, INT in_FRj,
				INT out_FRk)
{
  int cycles;
  INT dual_FRi;
  INT dual_FRj;
  INT dual_FRk;
  FRV_PROFILE_STATE *ps;
  FRV_VLIW *vliw;
  int slot;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  dual_FRi = DUAL_REG (in_FRi);
  dual_FRj = DUAL_REG (in_FRj);
  dual_FRk = DUAL_REG (out_FRk);

  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 14-15 in the LSI.  */
  adjust_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  vliw = CPU_VLIW (cpu);
  slot = vliw->next_slot - 1;
  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
  post_wait_for_media (cpu, slot);
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, dual_FRi);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, dual_FRj);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_FR (cpu, dual_FRk);

  /* Restore the busy cycles of the registers we used.  */
  restore_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2);

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing take 1 cycle.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_ptime (cpu, out_FRk, 1);
  set_use_is_fr_complex_1 (cpu, out_FRk);

  if (dual_FRk >= 0)
    {
      update_FR_latency (cpu, dual_FRk, ps->post_wait);
      update_FR_ptime (cpu, dual_FRk, 1);
      set_use_is_fr_complex_1 (cpu, dual_FRk);
    }

  /* the floating point unit resource has a latency of 3 cycles  */
  update_float_resource_latency (cpu, slot, cycles + 3);

  return cycles;
}

int
frvbf_model_fr550_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
				       int unit_num, int referenced,
				       INT in_FRi, INT out_FRk)
{
  int cycles;
  INT dual_FRk;
  FRV_PROFILE_STATE *ps;
  FRV_VLIW *vliw;
  int slot;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* If the previous use of the registers was a media op,
     then their latency will be less than previously recorded.
     See Table 14-15 in the LSI.  */
  dual_FRk = DUAL_REG (out_FRk);
  adjust_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, out_FRk, 2);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  vliw = CPU_VLIW (cpu);
  slot = vliw->next_slot - 1;
  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
  post_wait_for_media (cpu, slot);
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_FR (cpu, dual_FRk);

  /* Restore the busy cycles of the registers we used.  */
  restore_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, out_FRk, 2);

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_ptime (cpu, out_FRk, 1);
  set_use_is_fr_complex_1 (cpu, out_FRk);

  if (dual_FRk >= 0)
    {
      update_FR_latency (cpu, dual_FRk, ps->post_wait);
      update_FR_ptime (cpu, dual_FRk, 1);
      set_use_is_fr_complex_1 (cpu, dual_FRk);
    }

  /* the floating point unit resource has a latency of 3 cycles  */
  update_float_resource_latency (cpu, slot, cycles + 3);

  return cycles;
}

int
frvbf_model_fr550_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
				  int unit_num, int referenced,
				  INT in_FRi, INT out_FRk)
{
  int cycles;
  INT dual_FRi;
  FRV_PROFILE_STATE *ps;
  FRV_VLIW *vliw;
  int slot;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  dual_FRi = DUAL_REG (in_FRi);

  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 14-15 in the LSI.  */
  adjust_float_register_busy_for_media (cpu, in_FRi, 2, -1, 1, out_FRk, 1);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  vliw = CPU_VLIW (cpu);
  slot = vliw->next_slot - 1;
  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
  post_wait_for_media (cpu, slot);
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_FR (cpu, dual_FRi);
  post_wait_for_FR (cpu, out_FRk);

  /* Restore the busy cycles of the registers we used.  */
  restore_float_register_busy_for_media (cpu, in_FRi, 2, -1, 1, out_FRk, 1);

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing takes 1 cycle.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_ptime (cpu, out_FRk, 1);

  set_use_is_fr_complex_1 (cpu, out_FRk);

  /* the floating point unit resource has a latency of 3 cycles  */
  update_float_resource_latency (cpu, slot, cycles + 3);

  return cycles;
}

int
frvbf_model_fr550_u_media_3_acc (SIM_CPU *cpu, const IDESC *idesc,
				 int unit_num, int referenced,
				 INT in_FRj, INT in_ACC40Si,
				 INT out_FRk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  FRV_VLIW *vliw;
  int slot;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* If the previous use of the registers was a media op,
     then their latency will be less than previously recorded.
     See Table 14-15 in the LSI.  */
  adjust_float_register_busy_for_media (cpu, -1, 1, in_FRj, 1, out_FRk, 1);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  vliw = CPU_VLIW (cpu);
  slot = vliw->next_slot - 1;
  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
  post_wait_for_media (cpu, slot);
  post_wait_for_FR (cpu, in_FRj);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_ACC (cpu, in_ACC40Si);

  /* Restore the busy cycles of the registers we used.  */
  restore_float_register_busy_for_media (cpu, -1, 1, in_FRj, 1, out_FRk, 1);

  /* The latency of tht output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_ptime (cpu, out_FRk, 1);

  set_use_is_fr_complex_1 (cpu, out_FRk);

  /* the floating point unit resource has a latency of 3 cycles  */
  update_float_resource_latency (cpu, slot, cycles + 3);

  return cycles;
}

int
frvbf_model_fr550_u_media_3_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
				      int unit_num, int referenced,
				      INT in_ACC40Si, INT out_FRk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  INT ACC40Si_1;
  INT dual_FRk;
  FRV_VLIW *vliw;
  int slot;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ACC40Si_1 = DUAL_REG (in_ACC40Si);
  dual_FRk = DUAL_REG (out_FRk);

  /* If the previous use of the registers was a media op,
     then their latency will be less than previously recorded.
     See Table 14-15 in the LSI.  */
  adjust_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 2);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps = CPU_PROFILE_STATE (cpu);
  ps->post_wait = cycles;
  vliw = CPU_VLIW (cpu);
  slot = vliw->next_slot - 1;
  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
  post_wait_for_media (cpu, slot);
  post_wait_for_ACC (cpu, in_ACC40Si);
  post_wait_for_ACC (cpu, ACC40Si_1);
  post_wait_for_FR (cpu, out_FRk);
  post_wait_for_FR (cpu, dual_FRk);

  /* Restore the busy cycles of the registers we used.  */
  restore_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 2);

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  update_FR_latency (cpu, out_FRk, ps->post_wait);
  update_FR_ptime (cpu, out_FRk, 1);
  set_use_is_fr_complex_1 (cpu, out_FRk);
  if (dual_FRk >= 0)
    {
      update_FR_latency (cpu, dual_FRk, ps->post_wait);
      update_FR_ptime (cpu, dual_FRk, 1);
      set_use_is_fr_complex_1 (cpu, dual_FRk);
    }

  /* the floating point unit resource has a latency of 3 cycles  */
  update_float_resource_latency (cpu, slot, cycles + 3);

  return cycles;
}

int
frvbf_model_fr550_u_media_3_wtacc (SIM_CPU *cpu, const IDESC *idesc,
				   int unit_num, int referenced,
				   INT in_FRi, INT out_ACC40Sk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  FRV_VLIW *vliw;
  int slot;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ps = CPU_PROFILE_STATE (cpu);

  /* The latency of the registers may be less than previously recorded,
     depending on how they were used previously.
     See Table 14-15 in the LSI.  */
  adjust_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, -1, 1);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  vliw = CPU_VLIW (cpu);
  slot = vliw->next_slot - 1;
  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
  post_wait_for_media (cpu, slot);
  post_wait_for_FR (cpu, in_FRi);
  post_wait_for_ACC (cpu, out_ACC40Sk);

  /* Restore the busy cycles of the registers we used.  */
  restore_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, -1, 1);

  /* The latency of the output register will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait);
  update_ACC_ptime (cpu, out_ACC40Sk, 1);
  set_use_is_acc_mmac (cpu, out_ACC40Sk);

  /* the floating point unit resource has a latency of 3 cycles  */
  update_float_resource_latency (cpu, slot, cycles + 3);

  return cycles;
}

int
frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *cpu, const IDESC *idesc,
				     int unit_num, int referenced)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  FRV_VLIW *vliw;
  int slot;
  int i;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  ps = CPU_PROFILE_STATE (cpu);

  /* The post processing must wait if there is a dependency on a FR
     which is not ready yet.  */
  ps->post_wait = cycles;
  vliw = CPU_VLIW (cpu);
  slot = vliw->next_slot - 1;
  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
  post_wait_for_media (cpu, slot);

  /* If A was 1 and the accumulator was ACC0, then we must check all
     accumulators. Otherwise just wait for the specified accumulator.  */
  if (ps->mclracc_A && ps->mclracc_acc == 0)
    {
      for (i = 0; i < 8; ++i)
	post_wait_for_ACC (cpu, i);
    }
  else
    post_wait_for_ACC (cpu, ps->mclracc_acc);

  /* The latency of the output registers will be at least the latency of the
     other inputs.  Once initiated, post-processing will take 1 cycle.  */
  if (ps->mclracc_A && ps->mclracc_acc == 0)
    {
      for (i = 0; i < 8; ++i)
	{
	  update_ACC_latency (cpu, i, ps->post_wait);
	  update_ACC_ptime (cpu, i, 1);
	  set_use_is_acc_mmac (cpu, i);
	}
    }
  else
    {
      update_ACC_latency (cpu, ps->mclracc_acc, ps->post_wait);
      update_ACC_ptime (cpu, ps->mclracc_acc, 1);
      set_use_is_acc_mmac (cpu, ps->mclracc_acc);
    }

  /* the floating point unit resource has a latency of 3 cycles  */
  update_float_resource_latency (cpu, slot, cycles + 3);

  return cycles;
}

int
frvbf_model_fr550_u_media_set (SIM_CPU *cpu, const IDESC *idesc,
			       int unit_num, int referenced,
			       INT out_FRk)
{
  int cycles;
  FRV_PROFILE_STATE *ps;
  FRV_VLIW *vliw;
  int slot;

  if (model_insn == FRV_INSN_MODEL_PASS_1)
    return 0;

  /* The preprocessing can execute right away.  */
  cycles = idesc->timing->units[unit_num].done;

  /* If the previous use of the registers was a media op,
     then their latency will be less than previously recorded.
     See Table 14-15 in the LSI.  */
  adjust_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 1);

  /* The post processing m