profile-fr550.c

这个是LINUX下的GDB调度工具的源码

/* frv simulator fr550 dependent profiling code.

   Copyright (C) 2003 Free Software Foundation, Inc.
   Contributed by Red Hat

This file is part of the GNU simulators.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/
#define WANT_CPU
#define WANT_CPU_FRVBF

#include "sim-main.h"
#include "bfd.h"

#if WITH_PROFILE_MODEL_P

#include "profile.h"
#include "profile-fr550.h"

/* Initialize cycle counting for an insn.
   FIRST_P is non-zero if this is the first insn in a set of parallel
   insns.  */
void
fr550_model_insn_before (SIM_CPU *cpu, int first_p)
{
  if (first_p)
    {
      MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
      d->cur_fr_load      = d->prev_fr_load;
      d->cur_fr_complex_1 = d->prev_fr_complex_1;
      d->cur_fr_complex_2 = d->prev_fr_complex_2;
      d->cur_ccr_complex  = d->prev_ccr_complex;
      d->cur_acc_mmac     = d->prev_acc_mmac;
    }
}

/* Record the cycles computed for an insn.
   LAST_P is non-zero if this is the last insn in a set of parallel insns,
   and we update the total cycle count.
   CYCLES is the cycle count of the insn.  */
void
fr550_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
{
  if (last_p)
    {
      MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
      d->prev_fr_load      = d->cur_fr_load;
      d->prev_fr_complex_1 = d->cur_fr_complex_1;
      d->prev_fr_complex_2 = d->cur_fr_complex_2;
      d->prev_ccr_complex  = d->cur_ccr_complex;
      d->prev_acc_mmac     = d->cur_acc_mmac;
    }
}

static void fr550_reset_fr_flags (SIM_CPU *cpu, INT fr);
static void fr550_reset_ccr_flags (SIM_CPU *cpu, INT ccr);
static void fr550_reset_acc_flags (SIM_CPU *cpu, INT acc);

static void
set_use_is_fr_load (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  fr550_reset_fr_flags (cpu, (fr));
  d->cur_fr_load |= (((DI)1) << (fr));
}

static void
set_use_not_fr_load (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  d->cur_fr_load &= ~(((DI)1) << (fr));
}

static int
use_is_fr_load (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  return d->prev_fr_load & (((DI)1) << (fr));
}

static void
set_use_is_fr_complex_1 (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  fr550_reset_fr_flags (cpu, (fr));
  d->cur_fr_complex_1 |= (((DI)1) << (fr));
}

static void
set_use_not_fr_complex_1 (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  d->cur_fr_complex_1 &= ~(((DI)1) << (fr));
}

static int
use_is_fr_complex_1 (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  return d->prev_fr_complex_1 & (((DI)1) << (fr));
}

static void
set_use_is_fr_complex_2 (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  fr550_reset_fr_flags (cpu, (fr));
  d->cur_fr_complex_2 |= (((DI)1) << (fr));
}

static void
set_use_not_fr_complex_2 (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  d->cur_fr_complex_2 &= ~(((DI)1) << (fr));
}

static int
use_is_fr_complex_2 (SIM_CPU *cpu, INT fr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  return d->prev_fr_complex_2 & (((DI)1) << (fr));
}

static void
set_use_is_ccr_complex (SIM_CPU *cpu, INT ccr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  fr550_reset_ccr_flags (cpu, (ccr));
  d->cur_ccr_complex |= (((SI)1) << (ccr));
}

static void
set_use_not_ccr_complex (SIM_CPU *cpu, INT ccr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  d->cur_ccr_complex &= ~(((SI)1) << (ccr));
}

static int
use_is_ccr_complex (SIM_CPU *cpu, INT ccr)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  return d->prev_ccr_complex & (((SI)1) << (ccr));
}

static void
set_use_is_acc_mmac (SIM_CPU *cpu, INT acc)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  fr550_reset_acc_flags (cpu, (acc));
  d->cur_acc_mmac |= (((DI)1) << (acc));
}

static void
set_use_not_acc_mmac (SIM_CPU *cpu, INT acc)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  d->cur_acc_mmac &= ~(((DI)1) << (acc));
}

static int
use_is_acc_mmac (SIM_CPU *cpu, INT acc)
{
  MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
  return d->prev_acc_mmac & (((DI)1) << (acc));
}

static void
fr550_reset_fr_flags (SIM_CPU *cpu, INT fr)
{
  set_use_not_fr_load (cpu, fr);
  set_use_not_fr_complex_1 (cpu, fr);
  set_use_not_fr_complex_2 (cpu, fr);
}

static void
fr550_reset_ccr_flags (SIM_CPU *cpu, INT ccr)
{
  set_use_not_ccr_complex (cpu, ccr);
}

static void
fr550_reset_acc_flags (SIM_CPU *cpu, INT acc)
{
  set_use_not_acc_mmac (cpu, acc);
}

/* Detect overlap between two register ranges. Works if one of the registers
   is -1 with width 1 (i.e. undefined), but not both.  */
#define REG_OVERLAP(r1, w1, r2, w2) ( \
  (r1) + (w1) - 1 >= (r2) && (r2) + (w2) - 1 >= (r1) \
)

/* Latency of floating point registers may be less than recorded when followed
   by another floating point insn.  */
static void
adjust_float_register_busy (SIM_CPU *cpu,
			    INT in_FRi, int iwidth,
			    INT in_FRj, int jwidth,
			    INT out_FRk, int kwidth)
{
  int i;
  /* The latency of FRk may be less than previously recorded.
     See Table 14-15 in the LSI.  */
  if (in_FRi >= 0)
    {
      for (i = 0; i < iwidth; ++i)
	{
	  if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth))
	    if (use_is_fr_load (cpu, in_FRi + i))
	      decrease_FR_busy (cpu, in_FRi + i, 1);
	    else
	      enforce_full_fr_latency (cpu, in_FRi + i);
	}
    }

  if (in_FRj >= 0)
    {
      for (i = 0; i < jwidth; ++i)
	{
	  if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth)
	      && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth))
	    if (use_is_fr_load (cpu, in_FRj + i))
	      decrease_FR_busy (cpu, in_FRj + i, 1);
	    else
	      enforce_full_fr_latency (cpu, in_FRj + i);
	}
    }

  if (out_FRk >= 0)
    {
      for (i = 0; i < kwidth; ++i)
	{
	  if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth)
	      && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth))
	    {
	      if (use_is_fr_complex_1 (cpu, out_FRk + i))
		decrease_FR_busy (cpu, out_FRk + i, 1);
	      else if (use_is_fr_complex_2 (cpu, out_FRk + i))
		decrease_FR_busy (cpu, out_FRk + i, 2);
	      else
		enforce_full_fr_latency (cpu, out_FRk + i);
	    }
	}
    }
}

static void
restore_float_register_busy (SIM_CPU *cpu,
			     INT in_FRi, int iwidth,
			     INT in_FRj, int jwidth,
			     INT out_FRk, int kwidth)
{
  int i;
  /* The latency of FRk may be less than previously recorded.
     See Table 14-15 in the LSI.  */
  if (in_FRi >= 0)
    {
      for (i = 0; i < iwidth; ++i)
	{
	  if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth))
	    if (use_is_fr_load (cpu, in_FRi + i))
	      increase_FR_busy (cpu, in_FRi + i, 1);
	}
    }

  if (in_FRj >= 0)
    {
      for (i = 0; i < jwidth; ++i)
	{
	  if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth)
	      && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth))
	    if (use_is_fr_load (cpu, in_FRj + i))
	      increase_FR_busy (cpu, in_FRj + i, 1);
	}
    }

  if (out_FRk >= 0)
    {
      for (i = 0; i < kwidth; ++i)
	{
	  if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth)
	      && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth))
	    {
	      if (use_is_fr_complex_1 (cpu, out_FRk + i))
		increase_FR_busy (cpu, out_FRk + i, 1);
	      else if (use_is_fr_complex_2 (cpu, out_FRk + i))
		increase_FR_busy (cpu, out_FRk + i, 2);
	    }
	}
    }
}

/* Latency of floating point registers may be less than recorded when used in a
   media insns and followed by another media insn.  */
static void
adjust_float_register_busy_for_media (SIM_CPU *cpu,
				      INT in_FRi, int iwidth,
				      INT in_FRj, int jwidth,
				      INT out_FRk, int kwidth)
{
  int i;
  /* The latency of FRk may be less than previously recorded.
     See Table 14-15 in the LSI.  */
  if (out_FRk >= 0)
    {
      for (i = 0; i < kwidth; ++i)
	{
	  if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth)
	      && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth))
	    {
	      if (use_is_fr_complex_1 (cpu, out_FRk + i))
		decrease_FR_busy (cpu, out_FRk + i, 1);
	      else
		enforce_full_fr_latency (cpu, out_FRk + i);
	    }
	}
    }
}

static void
restore_float_register_busy_for_media (SIM_CPU *cpu,
				       INT in_FRi, int iwidth,
				       INT in_FRj, int jwidth,
				       INT out_FRk, int kwidth)
{
  int i;
  if (out_FRk >= 0)
    {
      for (i = 0; i < kwidth; ++i)
	{
	  if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth)
	      && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth))
	    {
	      if (use_is_fr_complex_1 (cpu, out_FRk + i))
		increase_FR_busy (cpu, out_FRk + i, 1);
	    }
	}
    }
}

/* Latency of accumulator registers may be less than recorded when used in a
   media insns and followed by another media insn.  */
static void
adjust_acc_busy_for_mmac (SIM_CPU *cpu,
			  INT in_ACC, int inwidth,
			  INT out_ACC, int outwidth)
{
  int i;
  /* The latency of an accumulator may be less than previously recorded.
     See Table 14-15 in the LSI.  */
  if (in_ACC >= 0)
    {
      for (i = 0; i < inwidth; ++i)
	{
	  if (use_is_acc_mmac (cpu, in_ACC + i))
	    decrease_ACC_busy (cpu, in_ACC + i, 1);
	  else
	    enforce_full_acc_latency (cpu, in_ACC + i);
	}
    }
  if (out_ACC >= 0)
    {
      for (i = 0; i < outwidth; ++i)
	{
	  if (! REG_OVERLAP (out_ACC + i, 1, in_ACC, inwidth))
	    {
	      if (use_is_acc_mmac (cpu, out_ACC + i))
		decrease_ACC_busy (cpu, out_ACC + i, 1);
	      else
		enforce_full_acc_latency (cpu, out_ACC + i);
	    }
	}
    }
}

static void
restore_acc_busy_for_mmac (SIM_CPU *cpu,
			   INT in_ACC, int inwidth,
			   INT out_ACC, int outwidth)
{
  int i;
  if (in_ACC >= 0)
    {
      for (i = 0; i < inwidth; ++i)
	{
	  if (use_is_acc_mmac (cpu, in_ACC + i))
	    increase_ACC_busy (cpu, in_ACC + i, 1);
	}
    }
  if (out_ACC >= 0)
    {
      for (i = 0; i < outwidth; ++i)
	{
	  if (! REG_OVERLAP (out_ACC + i, 1, in_ACC, inwidth))
	    {
	      if (use_is_acc_mmac (cpu, out_ACC + i))
		increase_ACC_busy (cpu, out_ACC + i, 1);
	    }
	}
    }
}

int
frvbf_model_fr550_u_exec (SIM_CPU *cpu, const IDESC *idesc,
			  int unit_num, int referenced)
{
  return idesc->timing->units[unit_num].done;
}

int
frvbf_model_fr550_u_integer (SIM_CPU *cpu, const IDESC *idesc,
			     int unit_num, int referenced,
			     INT in_GRi, INT in_GRj, INT out_GRk,
			     INT out_ICCi_1)
{
  int cycles;

  /* icc0-icc4 are the upper 4 fields of the CCR.  */
  if (out_ICCi_1 >= 0)
    out_ICCi_1 += 4;

  if (model_insn == FRV_INSN_MODEL_PASS_1)