cpu.h

这个是LINUX下的GDB调度工具的源码

/* CPU family header for frvbf.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996-2004 Free Software Foundation, Inc.

This file is part of the GNU simulators.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifndef CPU_FRVBF_H
#define CPU_FRVBF_H

/* Maximum number of instructions that are fetched at a time.
   This is for LIW type instructions sets (e.g. m32r).  */
#define MAX_LIW_INSNS 1

/* Maximum number of instructions that can be executed in parallel.  */
#define MAX_PARALLEL_INSNS 8

/* CPU state information.  */
typedef struct {
  /* Hardware elements.  */
  struct {
  /* program counter */
  USI h_pc;
#define GET_H_PC() CPU (h_pc)
#define SET_H_PC(x) (CPU (h_pc) = (x))
  /* PSR.IMPLE */
  UQI h_psr_imple;
#define GET_H_PSR_IMPLE() CPU (h_psr_imple)
#define SET_H_PSR_IMPLE(x) (CPU (h_psr_imple) = (x))
  /* PSR.VER */
  UQI h_psr_ver;
#define GET_H_PSR_VER() CPU (h_psr_ver)
#define SET_H_PSR_VER(x) (CPU (h_psr_ver) = (x))
  /* PSR.ICE bit */
  BI h_psr_ice;
#define GET_H_PSR_ICE() CPU (h_psr_ice)
#define SET_H_PSR_ICE(x) (CPU (h_psr_ice) = (x))
  /* PSR.NEM bit */
  BI h_psr_nem;
#define GET_H_PSR_NEM() CPU (h_psr_nem)
#define SET_H_PSR_NEM(x) (CPU (h_psr_nem) = (x))
  /* PSR.CM  bit */
  BI h_psr_cm;
#define GET_H_PSR_CM() CPU (h_psr_cm)
#define SET_H_PSR_CM(x) (CPU (h_psr_cm) = (x))
  /* PSR.BE  bit */
  BI h_psr_be;
#define GET_H_PSR_BE() CPU (h_psr_be)
#define SET_H_PSR_BE(x) (CPU (h_psr_be) = (x))
  /* PSR.ESR bit */
  BI h_psr_esr;
#define GET_H_PSR_ESR() CPU (h_psr_esr)
#define SET_H_PSR_ESR(x) (CPU (h_psr_esr) = (x))
  /* PSR.EF  bit */
  BI h_psr_ef;
#define GET_H_PSR_EF() CPU (h_psr_ef)
#define SET_H_PSR_EF(x) (CPU (h_psr_ef) = (x))
  /* PSR.EM  bit */
  BI h_psr_em;
#define GET_H_PSR_EM() CPU (h_psr_em)
#define SET_H_PSR_EM(x) (CPU (h_psr_em) = (x))
  /* PSR.PIL     */
  UQI h_psr_pil;
#define GET_H_PSR_PIL() CPU (h_psr_pil)
#define SET_H_PSR_PIL(x) (CPU (h_psr_pil) = (x))
  /* PSR.PS  bit */
  BI h_psr_ps;
#define GET_H_PSR_PS() CPU (h_psr_ps)
#define SET_H_PSR_PS(x) (CPU (h_psr_ps) = (x))
  /* PSR.ET  bit */
  BI h_psr_et;
#define GET_H_PSR_ET() CPU (h_psr_et)
#define SET_H_PSR_ET(x) (CPU (h_psr_et) = (x))
  /* PSR.S bit */
  BI h_psr_s;
#define GET_H_PSR_S() CPU (h_psr_s)
#define SET_H_PSR_S(x) \
do { \
frvbf_h_psr_s_set_handler (current_cpu, (x));\
;} while (0)
  /* TBR.TBA */
  USI h_tbr_tba;
#define GET_H_TBR_TBA() CPU (h_tbr_tba)
#define SET_H_TBR_TBA(x) (CPU (h_tbr_tba) = (x))
  /* TBR.TT */
  UQI h_tbr_tt;
#define GET_H_TBR_TT() CPU (h_tbr_tt)
#define SET_H_TBR_TT(x) (CPU (h_tbr_tt) = (x))
  /* PSR.S   bit */
  BI h_bpsr_bs;
#define GET_H_BPSR_BS() CPU (h_bpsr_bs)
#define SET_H_BPSR_BS(x) (CPU (h_bpsr_bs) = (x))
  /* PSR.ET  bit */
  BI h_bpsr_bet;
#define GET_H_BPSR_BET() CPU (h_bpsr_bet)
#define SET_H_BPSR_BET(x) (CPU (h_bpsr_bet) = (x))
  /* general registers */
  USI h_gr[64];
#define GET_H_GR(index) frvbf_h_gr_get_handler (current_cpu, index)
#define SET_H_GR(index, x) \
do { \
frvbf_h_gr_set_handler (current_cpu, (index), (x));\
;} while (0)
  /* floating point registers */
  SF h_fr[64];
#define GET_H_FR(index) frvbf_h_fr_get_handler (current_cpu, index)
#define SET_H_FR(index, x) \
do { \
frvbf_h_fr_set_handler (current_cpu, (index), (x));\
;} while (0)
  /* coprocessor registers */
  SI h_cpr[64];
#define GET_H_CPR(a1) CPU (h_cpr)[a1]
#define SET_H_CPR(a1, x) (CPU (h_cpr)[a1] = (x))
  /* special purpose registers */
  USI h_spr[4096];
#define GET_H_SPR(index) frvbf_h_spr_get_handler (current_cpu, index)
#define SET_H_SPR(index, x) \
do { \
frvbf_h_spr_set_handler (current_cpu, (index), (x));\
;} while (0)
  /* Integer condition code registers */
  UQI h_iccr[4];
#define GET_H_ICCR(a1) CPU (h_iccr)[a1]
#define SET_H_ICCR(a1, x) (CPU (h_iccr)[a1] = (x))
  /* Floating point condition code registers */
  UQI h_fccr[4];
#define GET_H_FCCR(a1) CPU (h_fccr)[a1]
#define SET_H_FCCR(a1, x) (CPU (h_fccr)[a1] = (x))
  /* Condition code registers */
  UQI h_cccr[8];
#define GET_H_CCCR(a1) CPU (h_cccr)[a1]
#define SET_H_CCCR(a1, x) (CPU (h_cccr)[a1] = (x))
  } hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} FRVBF_CPU_DATA;

/* Virtual regs.  */

#define GET_H_GR_DOUBLE(index) frvbf_h_gr_double_get_handler (current_cpu, index)
#define SET_H_GR_DOUBLE(index, x) \
do { \
frvbf_h_gr_double_set_handler (current_cpu, (index), (x));\
;} while (0)
#define GET_H_GR_HI(index) frvbf_h_gr_hi_get_handler (current_cpu, index)
#define SET_H_GR_HI(index, x) \
do { \
frvbf_h_gr_hi_set_handler (current_cpu, (index), (x));\
;} while (0)
#define GET_H_GR_LO(index) frvbf_h_gr_lo_get_handler (current_cpu, index)
#define SET_H_GR_LO(index, x) \
do { \
frvbf_h_gr_lo_set_handler (current_cpu, (index), (x));\
;} while (0)
#define GET_H_FR_DOUBLE(index) frvbf_h_fr_double_get_handler (current_cpu, index)
#define SET_H_FR_DOUBLE(index, x) \
do { \
frvbf_h_fr_double_set_handler (current_cpu, (index), (x));\
;} while (0)
#define GET_H_FR_INT(index) frvbf_h_fr_int_get_handler (current_cpu, index)
#define SET_H_FR_INT(index, x) \
do { \
frvbf_h_fr_int_set_handler (current_cpu, (index), (x));\
;} while (0)
#define GET_H_FR_HI(index) SRLSI (GET_H_FR_INT (index), 16)
#define SET_H_FR_HI(index, x) \
do { \
SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 65535), SLLHI ((x), 16)));\
;} while (0)
#define GET_H_FR_LO(index) ANDSI (GET_H_FR_INT (index), 65535)
#define SET_H_FR_LO(index, x) \
do { \
SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffff0000), ANDHI ((x), 65535)));\
;} while (0)
#define GET_H_FR_0(index) ANDSI (GET_H_FR_INT (index), 255)
#define SET_H_FR_0(index, x) \
do { \
{\
if (GTSI ((x), 255)) {\
  (x) = 255;\
}\
SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffffff00), (x)));\
}\
;} while (0)
#define GET_H_FR_1(index) ANDSI (SRLSI (GET_H_FR_INT (index), 8), 255)
#define SET_H_FR_1(index, x) \
do { \
{\
if (GTSI ((x), 255)) {\
  (x) = 255;\
}\
SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffff00ff), SLLHI ((x), 8)));\
}\
;} while (0)
#define GET_H_FR_2(index) ANDSI (SRLSI (GET_H_FR_INT (index), 16), 255)
#define SET_H_FR_2(index, x) \
do { \
{\
if (GTSI ((x), 255)) {\
  (x) = 255;\
}\
SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xff00ffff), SLLHI ((x), 16)));\
}\
;} while (0)
#define GET_H_FR_3(index) ANDSI (SRLSI (GET_H_FR_INT (index), 24), 255)
#define SET_H_FR_3(index, x) \
do { \
{\
if (GTSI ((x), 255)) {\
  (x) = 255;\
}\
SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 16777215), SLLHI ((x), 24)));\
}\
;} while (0)
#define GET_H_CPR_DOUBLE(index) frvbf_h_cpr_double_get_handler (current_cpu, index)
#define SET_H_CPR_DOUBLE(index, x) \
do { \
frvbf_h_cpr_double_set_handler (current_cpu, (index), (x));\
;} while (0)
#define GET_H_ACCG(index) ANDSI (GET_H_SPR (((index) + (1472))), 255)
#define SET_H_ACCG(index, x) \
do { \
CPU (h_spr[(((index)) + (1472))]) = ANDSI ((x), 255);\
;} while (0)
#define GET_H_ACC40S(index) ORDI (SLLDI (EXTQIDI (TRUNCSIQI (GET_H_SPR (((index) + (1472))))), 32), ZEXTSIDI (GET_H_SPR (((index) + (1408)))))
#define SET_H_ACC40S(index, x) \
do { \
{\
frv_check_spr_write_access (current_cpu, (((index)) + (1408)));\
CPU (h_spr[(((index)) + (1472))]) = ANDDI (SRLDI ((x), 32), 255);\
CPU (h_spr[(((index)) + (1408))]) = TRUNCDISI ((x));\
}\
;} while (0)
#define GET_H_ACC40U(index) ORDI (SLLDI (ZEXTSIDI (GET_H_SPR (((index) + (1472)))), 32), ZEXTSIDI (GET_H_SPR (((index) + (1408)))))
#define SET_H_ACC40U(index, x) \
do { \
{\
frv_check_spr_write_access (current_cpu, (((index)) + (1408)));\
CPU (h_spr[(((index)) + (1472))]) = ANDDI (SRLDI ((x), 32), 255);\
CPU (h_spr[(((index)) + (1408))]) = TRUNCDISI ((x));\
}\
;} while (0)
#define GET_H_IACC0(index) ORDI (SLLDI (EXTSIDI (GET_H_SPR (((UINT) 280))), 32), ZEXTSIDI (GET_H_SPR (((UINT) 281))))
#define SET_H_IACC0(index, x) \
do { \
{\
SET_H_SPR (((UINT) 280), TRUNCDISI (SRLDI ((x), 32)));\
SET_H_SPR (((UINT) 281), TRUNCDISI ((x)));\
}\
;} while (0)

/* Cover fns for register access.  */
USI frvbf_h_pc_get (SIM_CPU *);
void frvbf_h_pc_set (SIM_CPU *, USI);
UQI frvbf_h_psr_imple_get (SIM_CPU *);
void frvbf_h_psr_imple_set (SIM_CPU *, UQI);
UQI frvbf_h_psr_ver_get (SIM_CPU *);
void frvbf_h_psr_ver_set (SIM_CPU *, UQI);
BI frvbf_h_psr_ice_get (SIM_CPU *);
void frvbf_h_psr_ice_set (SIM_CPU *, BI);
BI frvbf_h_psr_nem_get (SIM_CPU *);
void frvbf_h_psr_nem_set (SIM_CPU *, BI);
BI frvbf_h_psr_cm_get (SIM_CPU *);
void frvbf_h_psr_cm_set (SIM_CPU *, BI);
BI frvbf_h_psr_be_get (SIM_CPU *);
void frvbf_h_psr_be_set (SIM_CPU *, BI);
BI frvbf_h_psr_esr_get (SIM_CPU *);
void frvbf_h_psr_esr_set (SIM_CPU *, BI);
BI frvbf_h_psr_ef_get (SIM_CPU *);
void frvbf_h_psr_ef_set (SIM_CPU *, BI);
BI frvbf_h_psr_em_get (SIM_CPU *);
void frvbf_h_psr_em_set (SIM_CPU *, BI);
UQI frvbf_h_psr_pil_get (SIM_CPU *);
void frvbf_h_psr_pil_set (SIM_CPU *, UQI);
BI frvbf_h_psr_ps_get (SIM_CPU *);
void frvbf_h_psr_ps_set (SIM_CPU *, BI);
BI frvbf_h_psr_et_get (SIM_CPU *);
void frvbf_h_psr_et_set (SIM_CPU *, BI);
BI frvbf_h_psr_s_get (SIM_CPU *);
void frvbf_h_psr_s_set (SIM_CPU *, BI);
USI frvbf_h_tbr_tba_get (SIM_CPU *);
void frvbf_h_tbr_tba_set (SIM_CPU *, USI);
UQI frvbf_h_tbr_tt_get (SIM_CPU *);
void frvbf_h_tbr_tt_set (SIM_CPU *, UQI);
BI frvbf_h_bpsr_bs_get (SIM_CPU *);
void frvbf_h_bpsr_bs_set (SIM_CPU *, BI);
BI frvbf_h_bpsr_bet_get (SIM_CPU *);
void frvbf_h_bpsr_bet_set (SIM_CPU *, BI);
USI frvbf_h_gr_get (SIM_CPU *, UINT);
void frvbf_h_gr_set (SIM_CPU *, UINT, USI);
DI frvbf_h_gr_double_get (SIM_CPU *, UINT);
void frvbf_h_gr_double_set (SIM_CPU *, UINT, DI);
UHI frvbf_h_gr_hi_get (SIM_CPU *, UINT);
void frvbf_h_gr_hi_set (SIM_CPU *, UINT, UHI);
UHI frvbf_h_gr_lo_get (SIM_CPU *, UINT);
void frvbf_h_gr_lo_set (SIM_CPU *, UINT, UHI);
SF frvbf_h_fr_get (SIM_CPU *, UINT);
void frvbf_h_fr_set (SIM_CPU *, UINT, SF);
DF frvbf_h_fr_double_get (SIM_CPU *, UINT);
void frvbf_h_fr_double_set (SIM_CPU *, UINT, DF);
USI frvbf_h_fr_int_get (SIM_CPU *, UINT);
void frvbf_h_fr_int_set (SIM_CPU *, UINT, USI);
UHI frvbf_h_fr_hi_get (SIM_CPU *, UINT);
void frvbf_h_fr_hi_set (SIM_CPU *, UINT, UHI);
UHI frvbf_h_fr_lo_get (SIM_CPU *, UINT);
void frvbf_h_fr_lo_set (SIM_CPU *, UINT, UHI);
UHI frvbf_h_fr_0_get (SIM_CPU *, UINT);
void frvbf_h_fr_0_set (SIM_CPU *, UINT, UHI);
UHI frvbf_h_fr_1_get (SIM_CPU *, UINT);
void frvbf_h_fr_1_set (SIM_CPU *, UINT, UHI);
UHI frvbf_h_fr_2_get (SIM_CPU *, UINT);
void frvbf_h_fr_2_set (SIM_CPU *, UINT, UHI);
UHI frvbf_h_fr_3_get (SIM_CPU *, UINT);
void frvbf_h_fr_3_set (SIM_CPU *, UINT, UHI);
SI frvbf_h_cpr_get (SIM_CPU *, UINT);
void frvbf_h_cpr_set (SIM_CPU *, UINT, SI);
DI frvbf_h_cpr_double_get (SIM_CPU *, UINT);
void frvbf_h_cpr_double_set (SIM_CPU *, UINT, DI);
USI frvbf_h_spr_get (SIM_CPU *, UINT);
void frvbf_h_spr_set (SIM_CPU *, UINT, USI);
USI frvbf_h_accg_get (SIM_CPU *, UINT);
void frvbf_h_accg_set (SIM_CPU *, UINT, USI);
DI frvbf_h_acc40S_get (SIM_CPU *, UINT);
void frvbf_h_acc40S_set (SIM_CPU *, UINT, DI);
UDI frvbf_h_acc40U_get (SIM_CPU *, UINT);
void frvbf_h_acc40U_set (SIM_CPU *, UINT, UDI);
DI frvbf_h_iacc0_get (SIM_CPU *, UINT);
void frvbf_h_iacc0_set (SIM_CPU *, UINT, DI);
UQI frvbf_h_iccr_get (SIM_CPU *, UINT);
void frvbf_h_iccr_set (SIM_CPU *, UINT, UQI);
UQI frvbf_h_fccr_get (SIM_CPU *, UINT);
void frvbf_h_fccr_set (SIM_CPU *, UINT, UQI);
UQI frvbf_h_cccr_get (SIM_CPU *, UINT);
void frvbf_h_cccr_set (SIM_CPU *, UINT, UQI);

/* These must be hand-written.  */
extern CPUREG_FETCH_FN frvbf_fetch_register;
extern CPUREG_STORE_FN frvbf_store_register;

typedef struct {
  int empty;
} MODEL_FRV_DATA;

typedef struct {
  DI prev_fr_load;
  DI prev_fr_complex_1;
  DI prev_fr_complex_2;
  DI prev_ccr_complex;
  DI prev_acc_mmac;
  DI cur_fr_load;
  DI cur_fr_complex_1;
  DI cur_fr_complex_2;
  SI cur_ccr_complex;
  DI cur_acc_mmac;
} MODEL_FR550_DATA;

typedef struct {
  DI prev_fpop;
  DI prev_media;
  DI prev_cc_complex;
  DI cur_fpop;
  DI cur_media;
  DI cur_cc_complex;
} MODEL_FR500_DATA;

typedef struct {
  int empty;
} MODEL_TOMCAT_DATA;

typedef struct {
  DI prev_fp_load;
  DI prev_fr_p4;
  DI prev_fr_p6;
  DI prev_acc_p2;
  DI prev_acc_p4;
  DI cur_fp_load;
  DI cur_fr_p4;
  DI cur_fr_p6;
  DI cur_acc_p2;
  DI cur_acc_p4;
} MODEL_FR400_DATA;

typedef struct {
  DI prev_fp_load;
  DI prev_fr_p4;
  DI prev_fr_p6;
  DI prev_acc_p2;
  DI prev_acc_p4;
  DI cur_fp_load;
  DI cur_fr_p4;
  DI cur_fr_p6;
  DI cur_acc_p2;
  DI cur_acc_p4;
} MODEL_FR450_DATA;

typedef struct {
  int empty;
} MODEL_SIMPLE_DATA;

/* Instruction argument buffer.  */

union sem_fields {
  struct { /* no operands */
    int empty;
  } fmt_empty;
  struct { /*  */
    unsigned short out_h_spr_USI_2;
  } sfmt_break;
  struct { /*  */
    UINT f_debug;
  } sfmt_rett;
  struct { /*  */
    IADDR i_label24;
  } sfmt_call;
  struct { /*  */
    INT f_u12;
    UINT f_FRk;