am33-2.igen

这个是LINUX下的GDB调度工具的源码

  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0110 0100 Sm1. Sm2. Sn.. XYZ-; fsub FSm1, FSm2, FSn
8.0xfb+8.0x64+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fsub
"fsub"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_sub (SD, CPU, cia,
	     &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
}

// 1111 1011 1110 0100 fm1- fm2- fn.- XYZ-; fsub FDm1, FDm2, FDn
8.0xfb+8.0xe4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fsub
"fsub"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}


// 1111 1110 0110 01YX Sm.. Sn.. IMM32; fsub imm32, FSm, FSn
8.0xfe+4.6,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fsub
"fsub"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);

      fpu_sub (SD, CPU, cia,
	       &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
    }
}

// 1111 1001 0111 00YX Sm.. Sn..; fmul FSm, FSn
8.0xf9+4.7,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fmul
"fmul"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_mul (SD, CPU, cia,
	     &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
}

// 1111 1001 1111 00YX fm.- fn.-; fmul FDm, FDn
8.0xf9+4.0xf,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fmul
"fmul"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0111 0000 Sm1. Sm2. Sn.. XYZ-; fmul FSm1, FSm2, FSn
8.0xfb+8.0x70+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fmul
"fmul"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_mul (SD, CPU, cia,
	     &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
}

// 1111 1011 1111 0000 fm1- fm2- fn.- XYZ-; fmul FDm1, FDm2, FDn
8.0xfb+8.0xf0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fmul
"fmul"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}


// 1111 1110 0111 00YX Sm.. Sn.. IMM32; fmul imm32, FSm, FSn
8.0xfe+4.7,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmul
"fmul"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);

      fpu_mul (SD, CPU, cia,
	       &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
    }
}

// 1111 1001 0111 01YX Sm.. Sn..; fdiv FSm, FSn
8.0xf9+4.7,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fdiv
"fdiv"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_div (SD, CPU, cia,
	     &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
}

// 1111 1001 1111 01YX fm.- fn.-; fdiv FDm, FDn
8.0xf9+4.0xf,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fdiv
"fdiv"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0111 0100 Sm1. Sm2. Sn.. XYZ-; fdiv FSm1, FSm2, FSn
8.0xfb+8.0x74+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fdiv
"fdiv"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_div (SD, CPU, cia,
	     &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
}

// 1111 1011 1111 0100 fm1- fm2- fn.- XYZ-; fdiv FDm1, FDm2, FDn
8.0xfb+8.0xf4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fdiv
"fdiv"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}


// 1111 1110 0111 01YX Sm.. Sn.. IMM32; fdiv imm32, FSm, FSn
8.0xfe+4.7,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fdiv
"fdiv"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);

      fpu_div (SD, CPU, cia,
	       &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
    }
}

// 1111 1011 1000 00Sn Sm1. Sm2. Sm3. XYZA; fmadd FSm1, FSm2, FSm3, FSn
8.0xfb+4.8,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmadd
"fmadd"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_fmadd (SD, CPU, cia,
	       &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
	       &AS2FS (A,Sn), FP_SINGLE);
}
    
// 1111 1011 1000 01Sn Sm1. Sm2. Sm3. XYZA; fmsub FSm1, FSm2, FSm3, FSn
8.0xfb+4.8,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmsub
"fmsub"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_fmsub (SD, CPU, cia,
	       &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
	       &AS2FS (A,Sn), FP_SINGLE);
}

// 1111 1011 1001 00Sn Sm1. Sm2. Sm3. XYZA; fnmadd FSm1, FSm2, FSm3, FSn
8.0xfb+4.9,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmadd
"fnmadd"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_fnmadd (SD, CPU, cia,
		&XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
		&AS2FS (A,Sn), FP_SINGLE);
}
    
// 1111 1011 1001 01Sn Sm1. Sm2. Sm3. XYZA; fnmsub FSm1, FSm2, FSm3, FSn
8.0xfb+4.9,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmsub
"fnmsub"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_fnmsub (SD, CPU, cia,
		&XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
		&AS2FS (A,Sn), FP_SINGLE);
}

// conversion:

// 1111 1011 0100 0000 Sm.. ---- Sn.. X-Z-; ftoi FSm,FSn
8.0xfb+8.0x40+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::ftoi
"ftoi"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0100 0010 Sm.. ---- Sn.. X-Z-; itof FSm,FSn
8.0xfb+8.0x42+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::itof
"itof"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0101 0010 Sm.. ---- fn.- X-Z-; ftod FSm,FDn
8.0xfb+8.0x52+4.Sm,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2:::ftod
"ftod"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0101 0110 fm.- ---- Sn.. X-Z-; dtof FDm,FSn
8.0xfb+8.0x56+3.fm,1.0,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::dtof
"dtof"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// branching:

// 1111 1000 1101 0000 d8; fbeq (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd0+8.D8:D1:::fbeq
"fbeq"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & FCC_E))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 0001 d8; fbne (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd1+8.D8:D1:::fbne
"fbne"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 0010 d8; fbgt (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd2+8.D8:D1:::fbgt
"fbgt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & FCC_G))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 0011 d8; fbge (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd3+8.D8:D1:::fbge
"fbge"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_G | FCC_E)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 0100 d8; fblt (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd4+8.D8:D1:::fblt
"fblt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & FCC_L))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 0101 d8; fble (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd5+8.D8:D1:::fble
"fble"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_L | FCC_E)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 0110 d8; fbuo (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd6+8.D8:D1:::fbuo
"fbuo"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & FCC_U))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 0111 d8; fblg (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd7+8.D8:D1:::fblg
"fblg"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_L | FCC_G)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}
// 1111 1000 1101 1000 d8; fbleg (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd8+8.D8:D1:::fbleg
"fbleg"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 1001 d8; fbug (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xd9+8.D8:D1:::fbug
"fbug"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_G)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 1010 d8; fbuge (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xda+8.D8:D1:::fbuge
"fbuge"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 1011 d8; fbul (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xdb+8.D8:D1:::fbul
"fbul"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_L)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 1100 d8; fbule (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xdc+8.D8:D1:::fbule
"fbule"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 1000 1101 1101 d8; fbue (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xdd+8.D8:D1:::fbue
"fbue"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_E)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}

// 1111 0000 1101 0000; fleq
8.0xf0+8.0xd0:D0:::fleq
"fleq"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & FCC_E))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 0001; flne
8.0xf0+8.0xd1:D0:::flne
"flne"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 0010; flgt
8.0xf0+8.0xd2:D0:::flgt
"flgt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & FCC_G))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 0011; flge
8.0xf0+8.0xd3:D0:::flge
"flge"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_G | FCC_E)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 0100; fllt
8.0xf0+8.0xd4:D0:::fllt
"fllt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & FCC_L))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 0101; flle
8.0xf0+8.0xd5:D0:::flle
"flle"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_L | FCC_E)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 0110; fluo
8.0xf0+8.0xd6:D0:::fluo
"fluo"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & FCC_U))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 0111; fllg
8.0xf0+8.0xd7:D0:::fllg
"fllg"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_L | FCC_G)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}
// 1111 0000 1101 1000; flleg
8.0xf0+8.0xd8:D0:::flleg
"flleg"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 1001; flug
8.0xf0+8.0xd9:D0:::flug
"flug"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_G)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 1010; fluge
8.0xf0+8.0xda:D0:::fluge
"fluge"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 1011; flul
8.0xf0+8.0xdb:D0:::flul
"flul"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_L)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 1100; flule
8.0xf0+8.0xdc:D0:::flule
"flule"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}

// 1111 0000 1101 1101; flue
8.0xf0+8.0xdd:D0:::flue
"flue"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else if ((FPCR & (FCC_U | FCC_E)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}