am33-2.igen

这个是LINUX下的GDB调度工具的源码

      int ri = translate_rreg (SD_, Ri);
      int rm = translate_rreg (SD_, Rm);
      Xf2FD (Z,fn) = load_dword (State.regs[ri] + State.regs[rm]);
    }
}
      
// 1111 1011 0101 0111 Ri.. Rn.. fm.- --Z-; fmov FDm,(Ri,Rn)
8.0xfb+8.0x57+4.Ri,4.Rn+3.fm,1.0,2.0,1.Z,1.0:D2j:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int ri = translate_rreg (SD_, Ri);
      int rn = translate_rreg (SD_, Rn);
      store_dword (State.regs[ri] + State.regs[rn], Xf2FD (Z,fm));
    }
}
      
// 1111 1011 1010 000X Rm.. fn.- d8; fmov (d8,Rm),FDn
8.0xfb+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM8:D2k:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
    }
}

// 1111 1011 1010 001X Rm.. fn.- d8; fmov (Rm+,imm8),FDn
8.0xfb+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM8:D2l:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
      State.regs[reg] += 8;
    }
}

// 1111 1011 1010 010X ---- fn.- d8; fmov (d8,SP),FDn
8.0xfb+4.0xa,3.2,1.X+4.0,4.fn+8.IMM8:D2m:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      Xf2FD (X, fn) = load_dword (State.regs[reg] + IMM8);
    }
}

// 1111 1011 1011 00Y0 fm.- Rn.. d8; fmov FDm,(d8,Rn)
8.0xfb+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM8:D2n:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
    }
}

// 1111 1011 1011 00Y1 fm.- Rn.. d8; fmov FDm,(Rn+,d8)
8.0xfb+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM8:D2o:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
      State.regs[reg] += 8;
    }
}

// 1111 1011 1011 01Y0 fm.- ---- d8; fmov FDm,(d8,SP)
8.0xfb+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM8:D2p:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      store_dword (State.regs[reg] + IMM8, Xf2FD (Y, fm));
    }
}

// 1111 1101 1010 000X Rm.. fn.- d24; fmov (d24,Rm),FDn
8.0xfd+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      Xf2FD (X, fn) = load_dword (State.regs[reg]
				  + EXTEND24 (FETCH24 (IMM24A,
						       IMM24B, IMM24C)));
    }
}

// 1111 1101 1010 001X Rm.. fn.- d24; fmov (Rm+,imm24),FDn
8.0xfd+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4l:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      Xf2FD (X, fn) = load_dword (State.regs[reg]
				  + EXTEND24 (FETCH24 (IMM24A,
						       IMM24B, IMM24C)));
      State.regs[reg] += 8;
    }
}

// 1111 1101 1010 010X ---- fn.- d24; fmov (d24,SP),FDn
8.0xfd+4.0xa,3.2,1.X+4.0,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4m:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      Xf2FD (X, fn) = load_dword (State.regs[reg]
				  + FETCH24 (IMM24A,
					     IMM24B, IMM24C));
    }
}

// 1111 1101 1011 00Y0 fm.- Rn.. d24; fmov FDm,(d24,Rn)
8.0xfd+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4n:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_dword (State.regs[reg]
		   + EXTEND24 (FETCH24 (IMM24A,
					IMM24B, IMM24C)), Xf2FD (Y, fm));
    }
}

// 1111 1101 1011 00Y1 fm.- Rn.. d24; fmov FDm,(Rn+,d24)
8.0xfd+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_dword (State.regs[reg]
		   + EXTEND24 (FETCH24 (IMM24A,
					IMM24B, IMM24C)), Xf2FD (Y, fm));
      State.regs[reg] += 8;
    }
}

// 1111 1101 1011 01Y0 fm.- ---- d24; fmov FDm,(d24,SP)
8.0xfd+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      store_dword (State.regs[reg] + FETCH24 (IMM24A,
					      IMM24B, IMM24C), Xf2FD (Y, fm));
    }
}

// 1111 1110 1010 000X Rm.. fn.- d32; fmov (d32,Rm),FDn
8.0xfe+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5k:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      Xf2FD (X, fn) = load_dword (State.regs[reg]
				  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
						       IMM32C, IMM32D)));
    }
}

// 1111 1110 1010 001X Rm.. fn.- d32; fmov (Rm+,imm32),FDn
8.0xfe+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5l:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      Xf2FD (X, fn) = load_dword (State.regs[reg]
				  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
						       IMM32C, IMM32D)));
      State.regs[reg] += 8;
    }
}

// 1111 1110 1010 010X ---- fn.- d32; fmov (d32,SP),FDn
8.0xfe+4.0xa,3.2,1.X+4.0,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5m:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      Xf2FD (X, fn) = load_dword (State.regs[reg]
				  + FETCH32 (IMM32A, IMM32B,
					     IMM32C, IMM32D));
    }
}

// 1111 1110 1011 00Y0 fm.- Rn.. d32; fmov FDm,(d32,Rn)
8.0xfe+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5n:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_dword (State.regs[reg]
		   + EXTEND32 (FETCH32 (IMM32A, IMM32B,
					IMM32C, IMM32D)), Xf2FD (Y, fm));
    }
}

// 1111 1110 1011 00Y1 fm.- Rn.. d32; fmov FDm,(Rn+,d32)
8.0xfe+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5o:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_dword (State.regs[reg]
		   + EXTEND32 (FETCH32 (IMM32A, IMM32B,
					IMM32C, IMM32D)), Xf2FD (Y, fm));
      State.regs[reg] += 8;
    }
}

// 1111 1110 1011 01Y0 fm.- ---- d32; fmov FDm,(d32,SP)
8.0xfe+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5p:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      store_dword (State.regs[reg]
		   + FETCH32 (IMM32A, IMM32B,
			      IMM32C, IMM32D), Xf2FD (Y, fm));
    }
}

// FPCR fmov:

// 1111 1001 1011 0101 Rm.. ----; fmov Rm,FPCR
8.0xf9+8.0xb5+4.Rm,4.0:D1q:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      unsigned32 val = State.regs[reg];
      FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
	| ((FPCR & ~val) & EF_MASK);
    }
}

// 1111 1001 1011 0111 ---- Rn..; fmov FPCR,Rn
8.0xf9+8.0xb7+4.0,4.Rn:D1r:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      State.regs[reg] = FPCR & FPCR_MASK;
    }
}

// 1111 1101 1011 0101 imm32; fmov imm32,FPCR
8.0xfd+8.0xb5+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
      FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
	| ((FPCR & ~val) & EF_MASK);
    }
}

// fabs:

// 1111 1001 0100 010X ---- Sn..; fabs FSn
8.0xf9+4.4,3.2,1.X+4.0,4.Sn:D1a:::fabs
"fabs"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      sim_fpu in, out;

      FS2FPU (XS2FS (X,Sn), in);
      sim_fpu_abs (&out, &in);
      FPU2FS (out, XS2FS (X,Sn));
    }
}

// 1111 1001 1100 010X ---- Sn..; fabs FDn
8.0xf9+4.0xc,3.2,1.X+4.0,3.fn,1.0:D1b:::fabs
"fabs"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0100 0100 Sm.. ---- Sn.. X-Z-; fabs FSm,FSn
8.0xfb+8.0x44+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fabs
"fabs"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      sim_fpu in, out;

      FS2FPU (XS2FS (X,Sm), in);
      sim_fpu_abs (&out, &in);
      FPU2FS (out, XS2FS (Z,Sn));
    }
}

// 1111 1011 1100 0100 fm.- ---- fn.- X-Z-; fabs FDm,FDn
8.0xfb+8.0xc4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fabs
"fabs"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1001 0100 011X ---- Sn..; fneg FSn
8.0xf9+4.4,3.3,1.X+4.0,4.Sn:D1a:::fneg
"fneg"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      sim_fpu in, out;

      FS2FPU (XS2FS (X,Sn), in);
      sim_fpu_neg (&out, &in);
      FPU2FS (out, XS2FS (X,Sn));
    }
}

// 1111 1001 1100 011X ---- Sn..; fneg FDn
8.0xf9+4.0xc,3.3,1.X+4.0,3.fn,1.0:D1b:::fneg
"fneg"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0100 0110 Sm.. ---- Sn.. X-Z-; fneg FSm,FSn
8.0xfb+8.0x46+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fneg
"fneg"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      sim_fpu in, out;

      FS2FPU (XS2FS (X,Sm), in);
      sim_fpu_neg (&out, &in);
      FPU2FS (out, XS2FS (Z,Sn));
    }
}

// 1111 1011 1100 0110 fm.- ---- fn.- X-Z-; fneg FDm,FDn
8.0xfb+8.0xc6+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fneg
"fneg"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1001 0101 000X ---- Sn..; frsqrt FSn
8.0xf9+4.5,3.0,1.X+4.0,4.Sn:D1a:::frsqrt
"frsqrt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
}

// 1111 1001 1101 000X ---- fn.-; frsqrt FDn
8.0xf9+4.0xd,3.0,1.X+4.0,3.fn,1.0:D1b:::frsqrt
"frsqrt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0101 0000 Sm.. ---- Sn.. X-Z-; frsqrt FSm,FSn
8.0xfb+8.0x50+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::frsqrt
"frsqrt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sm), &XS2FS (Z,Sn), FP_SINGLE);
}

// 1111 1011 1101 0000 fm.- ---- fn.- X-Z-; frsqrt FDm,FDn
8.0xfb+8.0xd0+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::frsqrt
"frsqrt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1001 0101 001X ---- Sn..; fsqrt FSn
8.0xf9+4.5,3.1,1.X+4.0,4.Sn:D1a:::fsqrt
"fsqrt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1001 1101 001X ---- fn.-; fsqrt FDn
8.0xf9+4.0xd,3.1,1.X+4.0,3.fn,1.0:D1b:::fsqrt
"fsqrt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0101 0100 Sm.. ---- Sn.. X-Z-; fsqrt FSm,FSn
8.0xfb+8.0x54+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fsqrt
"fsqrt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 1101 0100 fm.- ---- fn.- X-Z-; fsqrt FDm,FDn
8.0xfb+8.0xd4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fsqrt
"fsqrt"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1001 0101 01YX Sm.. Sn..; fcmp FSm, FSn
8.0xf9+4.5,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fcmp
"fcmp"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_cmp (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (Y,Sm), FP_SINGLE);
}

// 1111 1001 1101 01YX fm.- fn.-; fcmp FDm, FDn
8.0xf9+4.0xd,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fcmp
"fcmp"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1110 0011 01Y1 Sm.. ---- IMM32; fcmp imm32, FSm
8.0xfe+4.3,2.1,1.Y,1.1+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fcmp
"fcmp"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);

      fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
    }
}

// 1111 1001 0110 00YX Sm.. Sn..; fadd FSm, FSn
8.0xf9+4.6,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fadd
"fadd"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_add (SD, CPU, cia,
	     &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
}

// 1111 1001 1110 00YX fm.- fn.-; fadd FDm, FDn
8.0xf9+4.0xe,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fadd
"fadd"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0110 0000 Sm1. Sm2. Sn.. XYZ-; fadd FSm1, FSm2, FSn
8.0xfb+8.0x60+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fadd
"fadd"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_add (SD, CPU, cia,
	     &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
}

// 1111 1011 1110 0000 fm1- fm2- fn.- XYZ-; fadd FDm1, FDm2, FDn
8.0xfb+8.0xe0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fadd
"fadd"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}


// 1111 1110 0110 00YX Sm.. Sn.. IMM32; fadd imm32, FSm, FSn
8.0xfe+4.6,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fadd
"fadd"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);

      fpu_add (SD, CPU, cia,
	       &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
    }
}

// 1111 1001 0110 01YX Sm.. Sn..; fsub FSm, FSn
8.0xf9+4.6,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fsub
"fsub"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_sub (SD, CPU, cia,
	     &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
}

// 1111 1001 1110 01YX fm.- fn.-; fsub FDm, FDn
8.0xf9+4.0xe,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fsub
"fsub"
*am33_2
{