am33-2.igen

这个是LINUX下的GDB调度工具的源码

// data cache pre-fetch:

// 1111 1001 1010 0110 Rm.. 0000; dcpf (Rm)
8.0xf9+8.0xa6+4.RN2,4.0000:D1a:::dcpf
"dcpf"
*am33_2
{
  int srcreg;

  PC = cia;

  srcreg = translate_rreg (SD_, RN2);
  load_word (State.regs[srcreg]);
}

// 1111 1001 1010 0111 0000 0000; dcpf (sp)
8.0xf9+8.0xa7+8.0x00:D1b:::dcpf
"dcpf"
*am33_2
{
  PC = cia;

  load_word (SP);
}

// 1111 1011 1010 0110 Ri.. Rm.. 0000 0000; dcpf (Ri,Rm)
8.0xfb+8.0xa6+4.RN2,4.RN0+8.0x00:D2a:::dcpf
"dcpf"
*am33_2
{
  int srci, srcm;

  PC = cia;

  srci = translate_rreg (SD_, RN2);
  srcm = translate_rreg (SD_, RN0);

  load_word (State.regs[srci] + State.regs[srcm]);
}

// 1111 1011 1010 0111 Rm.. 0000 IMM8; dcpf (d8,Rm)
8.0xfb+8.0xa7+4.RN2,4.0000+8.IMM8:D2b:::dcpf
"dcpf"
*am33_2
{
  int srcreg;

  PC = cia;

  srcreg = translate_rreg (SD_, RN2);

  load_word (State.regs[srcreg] + EXTEND8 (IMM8));
}

// 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
8.0xfd+8.0xa7+4.RN2,4.0000+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::dcpf
"dcpf"
*am33_2
{
  int srcreg;

  PC = cia;

  srcreg = translate_rreg (SD_, RN2);

  load_word (State.regs[srcreg] + EXTEND24 (FETCH24 (IMM24A,
						     IMM24B, IMM24C)));
}

// 1111 1110 0100 0110 Rm.. 0000 IMM32; dcpf (d32,Rm)
8.0xfe+8.0x46+4.RN2,4.0000+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::dcpf
"dcpf"
*am33_2
{
  int srcreg;

  PC = cia;

  srcreg = translate_rreg (SD_, RN2);

  load_word (State.regs[srcreg]
	     + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}

// bit operations with imm8,(abs16) addressing mode:

// 1111 1110 1000 0010 ABS16 IMM8; btst imm8,(abs16)
8.0xfe+8.0x82+8.IMM16A+8.IMM16B+8.IMM8:D3:::btst
"btst"
*am33_2
{
  PC = cia;
  genericBtst (IMM8, FETCH16 (IMM16A, IMM16B));
}

// 1111 1110 1000 0000 ABS16 IMM8; bset imm8,(abs16)
8.0xfe+8.0x80+8.IMM16A+8.IMM16B+8.IMM8:D3:::bset
"bset"
*am33_2
{
  unsigned32 temp;
  int z;
  
  PC = cia;
  temp = load_byte (FETCH16 (IMM16A, IMM16B));
  z = (temp & IMM8) == 0;
  temp |= IMM8;
  store_byte (FETCH16 (IMM16A, IMM16B), temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}

// 1111 1110 1000 0001 ABS16 IMM8; bclr imm8,(abs16)
8.0xfe+8.0x81+8.IMM16A+8.IMM16B+8.IMM8:D3:::bclr
"bclr"
*am33_2
{
  unsigned32 temp;
  int z;
  
  PC = cia;
  temp = load_byte (FETCH16 (IMM16A, IMM16B));
  z = (temp & IMM8) == 0;
  temp = temp & ~(IMM8);
  store_byte (FETCH16 (IMM16A, IMM16B), temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}

// single precision fmov:

// 1111 1001 0010 000X Rm.. Sn..; fmov (Rm),FSn
8.0xf9+4.2,3.0,1.X+4.Rm,4.Sn:D1a:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X,Sn) = load_word (State.regs[reg]);
    }
}

// 1111 1001 0010 001X Rm.. Sn..; fmov (Rm+),FSn
8.0xf9+4.2,3.1,1.X+4.Rm,4.Sn:D1b:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X,Sn) = load_word (State.regs[reg]);
      State.regs[reg] += 4;
    }
}

// 1111 1001 0010 010X ---- Sn..; fmov (SP),FSn
8.0xf9+4.2,3.2,1.X+4.0,4.Sn:D1c:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      XS2FS (X,Sn) = load_word (State.regs[reg]);
    }
}

// 1111 1001 0010 011X Rm.. Sn..; fmov Rm,FSn
8.0xf9+4.2,3.3,1.X+4.Rm,4.Sn:D1d:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X,Sn) = State.regs[reg];
    }
}

// 1111 1001 0011 00Y0 Sm.. Rn..; fmov FSm,(Rn)
8.0xf9+4.3,2.0,1.Y,1.0+4.Sm,4.Rn:D1e:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_word (State.regs[reg], XS2FS (Y,Sm));
    }
}

// 1111 1001 0011 00Y1 Sm.. Rn..; fmov FSm,(Rn+)
8.0xf9+4.3,2.0,1.Y,1.1+4.Sm,4.Rn:D1f:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_word (State.regs[reg], XS2FS (Y,Sm));
      State.regs[reg] += 4;
    }
}

// 1111 1001 0011 01Y0 Sm.. ----; fmov FSm,(SP)
8.0xf9+4.3,2.1,1.Y,1.0+4.Sm,4.0:D1g:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      store_word (State.regs[reg], XS2FS (Y,Sm));
    }
}

// 1111 1001 0011 01Y1 Sm.. Rn..; fmov FSm,Rn
8.0xf9+4.3,2.1,1.Y,1.1+4.Sm,4.Rn:D1h:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      State.regs[reg] = XS2FS (Y,Sm);
    }
}

// 1111 1001 0100 00YX Sm.. Sn..; fmov FSm,FSn
8.0xf9+4.4,2.0,1.Y,1.X+4.Sm,4.Sn:D1i:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    XS2FS (X,Sn) = XS2FS (Y,Sm);
}

// 1111 1011 0010 000X Rm.. Sn.. d8; fmov (d8,Rm),FSn
8.0xfb+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM8:D2a:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
    }
}

// 1111 1011 0010 001X Rm.. Sn.. d8; fmov (Rm+,imm8),FSn
8.0xfb+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM8:D2b:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
      State.regs[reg] += 4;
    }
}

// 1111 1011 0010 010X ---- Sn.. d8; fmov (d8,SP),FSn
8.0xfb+4.2,3.2,1.X+4.0,4.Sn+8.IMM8:D2c:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      XS2FS (X, Sn) = load_word (State.regs[reg] + IMM8);
    }
}

// 1111 1011 0010 0111 Ri.. Rm.. Sn.. --Z-; fmov (Ri,Rm),FSn
8.0xfb+8.0x27+4.Ri,4.Rm+4.Sn,2.0,1.Z,1.0:D2d:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int ri = translate_rreg (SD_, Ri);
      int rm = translate_rreg (SD_, Rm);
      XS2FS (Z, Sn) = load_word (State.regs[ri] + State.regs[rm]);
    }
}

// 1111 1011 0011 00Y0 Sm.. Rn.. d8; fmov FSm,(d8,Rn)
8.0xfb+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM8:D2e:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
    }
}

// 1111 1011 0011 00Y1 Sm.. Rn.. d8; fmov FSm,(Rn+,d8)
8.0xfb+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM8:D2f:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
      State.regs[reg] += 4;
    }
}

// 1111 1011 0011 01Y0 Sm.. ---- d8; fmov FSm,(d8,SP)
8.0xfb+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM8:D2g:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      store_word (State.regs[reg] + IMM8, XS2FS (Y, Sm));
    }
}

// 1111 1011 0011 0111 Ri.. Rm.. Sm.. --Z-; fmov FSm,(Ri,Rm)
8.0xfb+8.0x37+4.Ri,4.Rm+4.Sm,2.0,1.Z,1.0:D2h:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int ri = translate_rreg (SD_, Ri);
      int rm = translate_rreg (SD_, Rm);
      store_word (State.regs[ri] + State.regs[rm], XS2FS (Z, Sm));
    }
}

// 1111 1101 0010 000X Rm.. Sn.. d24; fmov (d24,Rm),FSn
8.0xfd+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X, Sn) = load_word (State.regs[reg]
				 + EXTEND24 (FETCH24 (IMM24A,
						      IMM24B, IMM24C)));
    }
}

// 1111 1101 0010 001X Rm.. Sn.. d24; fmov (Rm+,imm24),FSn
8.0xfd+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X, Sn) = load_word (State.regs[reg]
				 + EXTEND24 (FETCH24 (IMM24A,
						      IMM24B, IMM24C)));
      State.regs[reg] += 4;
    }
}

// 1111 1101 0010 010X ---- Sn.. d24; fmov (d24,SP),FSn
8.0xfd+4.2,3.2,1.X+4.0,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      XS2FS (X, Sn) = load_word (State.regs[reg] + FETCH24 (IMM24A,
							    IMM24B, IMM24C));
    }
}

// 1111 1101 0011 00Y0 Sm.. Rn.. d24; fmov FSm,(d24,Rn)
8.0xfd+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4e:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_word (State.regs[reg]
		  + EXTEND24 (FETCH24 (IMM24A,
				       IMM24B, IMM24C)), XS2FS (Y, Sm));
    }
}

// 1111 1101 0011 00Y1 Sm.. Rn.. d24; fmov FSm,(Rn+,d24)
8.0xfd+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4f:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_word (State.regs[reg]
		  + EXTEND24 (FETCH24 (IMM24A,
				       IMM24B, IMM24C)), XS2FS (Y, Sm));
      State.regs[reg] += 4;
    }
}

// 1111 1101 0011 01Y0 Sm.. ---- d24; fmov FSm,(d24,SP)
8.0xfd+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4g:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      store_word (State.regs[reg]
		  + FETCH24 (IMM24A,
			     IMM24B, IMM24C), XS2FS (Y, Sm));
    }
}

// 1111 1110 0010 000X Rm.. Sn.. d32; fmov (d32,Rm),FSn
8.0xfe+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X, Sn) = load_word (State.regs[reg]
				 + EXTEND32 (FETCH32 (IMM32A, IMM32B,
						      IMM32C, IMM32D)));
    }
}

// 1111 1110 0010 001X Rm.. Sn.. d32; fmov (Rm+,imm32),FSn
8.0xfe+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      XS2FS (X, Sn) = load_word (State.regs[reg]
				 + EXTEND32 (FETCH32 (IMM32A, IMM32B,
						      IMM32C, IMM32D)));
      State.regs[reg] += 4;
    }
}

// 1111 1110 0010 010X ---- Sn.. d32; fmov (d32,SP),FSn
8.0xfe+4.2,3.2,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      XS2FS (X, Sn) = load_word (State.regs[reg]
				 + FETCH32 (IMM32A, IMM32B,
					    IMM32C, IMM32D));
    }
}

// 1111 1110 0010 011X ---- Sn.. d32; fmov imm32,FSn
8.0xfe+4.2,3.3,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    XS2FS (X, Sn) = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
}

// 1111 1110 0011 00Y0 Sm.. Rn.. d32; fmov FSm,(d32,Rn)
8.0xfe+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_word (State.regs[reg]
		  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
				       IMM32C, IMM32D)), XS2FS (Y, Sm));
    }
}

// 1111 1110 0011 00Y1 Sm.. Rn.. d32; fmov FSm,(Rn+,d32)
8.0xfe+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_word (State.regs[reg]
		  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
				       IMM32C, IMM32D)), XS2FS (Y, Sm));
      State.regs[reg] += 4;
    }
}

// 1111 1110 0011 01Y0 Sm.. ---- d32; fmov FSm,(d32,SP)
8.0xfe+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      store_word (State.regs[reg]
		  + FETCH32 (IMM32A, IMM32B,
			     IMM32C, IMM32D), XS2FS (Y, Sm));
    }
}

// double precision fmov:

// 1111 1001 1010 000X Rm.. fn.-; fmov (Rm),FDn
8.0xf9+4.0xa,3.0,1.X+4.Rm,3.fn,1.0:D1j:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      Xf2FD (X,fn) = load_dword (State.regs[reg]);
    }
}

// 1111 1001 1010 001X Rm.. fn.-; fmov (Rm+),FDn
8.0xf9+4.0xa,3.1,1.X+4.Rm,3.fn,1.0:D1k:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rm);
      Xf2FD (X,fn) = load_dword (State.regs[reg]);
      State.regs[reg] += 8;
    }
}

// 1111 1001 1010 010X ---- fn.-; fmov (SP),FDn
8.0xf9+4.0xa,3.2,1.X+4.0,3.fn,1.0:D1l:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      Xf2FD (X,fn) = load_dword (State.regs[reg]);
    }
}

// 1111 1001 1011 00Y0 fm.- Rn..; fmov FDm,(Rn)
8.0xf9+4.0xb,2.0,1.Y,1.0+3.fm,1.0,4.Rn:D1m:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_dword (State.regs[reg], Xf2FD (Y,fm));
    }
}

// 1111 1001 1011 00Y1 fm.- Rn..; fmov FDm,(Rn+)
8.0xf9+4.0xb,2.0,1.Y,1.1+3.fm,1.0,4.Rn:D1n:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = translate_rreg (SD_, Rn);
      store_dword (State.regs[reg], Xf2FD (Y,fm));
      State.regs[reg] += 8;
    }
}

// 1111 1001 1011 01Y0 fm.- ----; fmov FDm,(SP)
8.0xf9+4.0xb,2.1,1.Y,1.0+3.fm,1.0,4.0:D1o:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {
      int reg = REG_SP;
      store_dword (State.regs[reg], Xf2FD (Y,fm));
    }
}

// 1111 1001 1100 00YX fm.- fn.-; fmov FDm,FDn
8.0xf9+4.0xc,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1p:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    fpu_unimp_exception (SD, CPU, cia);
}

// 1111 1011 0100 0111 Ri.. Rm.. fn.- --Z-; fmov (Ri,Rm),FDn
8.0xfb+8.0x47+4.Ri,4.Rm+3.fn,1.0,2.0,1.Z,1.0:D2i:::fmov
"fmov"
*am33_2
{
  PC = cia;

  if (FPU_DISABLED)
    fpu_disabled_exception (SD, CPU, cia);
  else
    {