mn10300.igen

这个是LINUX下的GDB调度工具的源码

*am33
*am33_2

{
  /* OP_C400 (); */
  PC = cia;
  if (PSW & PSW_C)
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xe8+8.D8:D1:::bvc
"bvc"
*mn10300

*am33
*am33_2

{
  /* OP_F8E800 (); */
  PC = cia;
  if (!(PSW & PSW_V))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xe9+8.D8:D1:::bvs
"bvs"
*mn10300

*am33
*am33_2

{
  /* OP_F8E900 (); */
  PC = cia;
  if (PSW & PSW_V)
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xea+8.D8:D1:::bnc
"bnc"
*mn10300

*am33
*am33_2

{
  /* OP_F8EA00 (); */
  PC = cia;
  if (!(PSW & PSW_N))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
8.0xf8+8.0xeb+8.D8:D1:::bns
"bns"
*mn10300

*am33
*am33_2

{
  /* OP_F8EB00 (); */
  PC = cia;
  if (PSW & PSW_N)
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
8.0xca+8.D8:S1:::bra
"bra"
*mn10300

*am33
*am33_2

{
  /* OP_CA00 (); */
  PC = cia;
  State.regs[REG_PC] += EXTEND8 (D8);
  nia = PC;
}


// 1101 1000; leq
8.0xd8:S0:::leq
"leq"
*mn10300

*am33
*am33_2

{
  /* OP_D8 (); */
  PC = cia;
  if (PSW & PSW_Z)
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 1001; lne
8.0xd9:S0:::lne
"lne"
*mn10300

*am33
*am33_2

{
  /* OP_D9 (); */
  PC = cia;
  if (!(PSW & PSW_Z))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 0001; lgt
8.0xd1:S0:::lgt
"lgt"
*mn10300

*am33
*am33_2

{
  /* OP_D1 (); */
  PC = cia;
  if (!((PSW & PSW_Z)
        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 0010; lge
8.0xd2:S0:::lge
"lge"
*mn10300

*am33
*am33_2

{
  /* OP_D2 (); */
  PC = cia;
  if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 0011; lle
8.0xd3:S0:::lle
"lle"
*mn10300

*am33
*am33_2

{
  /* OP_D3 (); */
  PC = cia;
  if ((PSW & PSW_Z)
      || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 0000; llt
8.0xd0:S0:::llt
"llt"
*mn10300

*am33
*am33_2

{
  /* OP_D0 (); */
  PC = cia;
  if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 0101; lhi
8.0xd5:S0:::lhi
"lhi"
*mn10300

*am33
*am33_2

{
  /* OP_D5 (); */
  PC = cia;
  if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 0110; lcc
8.0xd6:S0:::lcc
"lcc"
*mn10300

*am33
*am33_2

{
  /* OP_D6 (); */
  PC = cia;
  if (!(PSW & PSW_C))
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 0111; lls
8.0xd7:S0:::lls
"lls"
*mn10300

*am33
*am33_2

{
  /* OP_D7 (); */
  PC = cia;
  if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 0100; lcs
8.0xd4:S0:::lcs
"lcs"
*mn10300

*am33
*am33_2

{
  /* OP_D4 (); */
  PC = cia;
  if (PSW & PSW_C)
    {
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
      nia = PC;
    }
}


// 1101 1010; lra
8.0xda:S0:::lra
"lra"
*mn10300

*am33
*am33_2

{
  /* OP_DA (); */
  PC = cia;
  State.regs[REG_PC] = State.regs[REG_LAR] - 4;
  nia = PC;
}


// 1101 1010; setlb
8.0xdb:S0:::setlb
"setlb"
*mn10300

*am33
*am33_2

{
  /* OP_DB (); */
  PC = cia;
  State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
  State.regs[REG_LAR] = State.regs[REG_PC] + 5;
}


// 1111 0000 1111 01An; jmp (An)
8.0xf0+4.0xf,01,2.AN0:D0:::jmp
"jmp"
*mn10300

*am33
*am33_2

{
  /* OP_F0F4 (); */
  PC = State.regs[REG_A0 + AN0];
  nia = PC;
}


// 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
8.0xcc+8.D16A+8.D16B:S2:::jmp
"jmp"
*mn10300

*am33
*am33_2

{
  /* OP_CC0000 (); */
  PC = cia + EXTEND16(FETCH16(D16A, D16B));
  nia = PC;
}


// 1101 1100 d32........; jmp (d32, PC)
8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
"jmp"
*mn10300

*am33
*am33_2

{
  /* OP_DC000000 (); */
  PC = cia + FETCH32(D32A, D32B, D32C, D32D);
  nia = PC;
}


// 1111 0000 1111 00An; calls (An)
8.0xf0+4.0xf,00,2.AN0:D0:::calls
"calls"
*mn10300

*am33
*am33_2

{
  /* OP_F0F0 (); */
  unsigned32 next_pc, sp;

  PC = cia;
  sp = State.regs[REG_SP];
  next_pc = State.regs[REG_PC] + 2;
  store_word(sp, next_pc);
  State.regs[REG_MDR] = next_pc;
  State.regs[REG_PC] = State.regs[REG_A0 + AN0];
  nia = PC;
}


// 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
"calls"
*mn10300

*am33
*am33_2

{
  /* OP_FAFF0000 (); */
  unsigned32 next_pc, sp;

  PC = cia;
  sp = State.regs[REG_SP];
  next_pc = State.regs[REG_PC] + 4;
  store_word(sp, next_pc);
  State.regs[REG_MDR] = next_pc;
  State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
  nia = PC;
}


// 1111 1100 1111 1111 d32.....; calls (d32,PC)
8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
"calls"
*mn10300

*am33
*am33_2

{
  /* OP_FCFF0000 (); */
  unsigned32 next_pc, sp;

  PC = cia;
  sp = State.regs[REG_SP];
  next_pc = State.regs[REG_PC] + 6;
  store_word(sp, next_pc);
  State.regs[REG_MDR] = next_pc;
  State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
  nia = PC;
}


// 1111 0000 1111 1100; rets
8.0xf0+8.0xfc:D0:::rets
"rets"
*mn10300

*am33
*am33_2

{
  /* OP_F0FC (); */
  unsigned32 sp;

  sp = State.regs[REG_SP];
  State.regs[REG_PC] = load_word(sp);
  nia = PC;
}


// 1111 0000 1111 1101; rti
8.0xf0+8.0xfd:D0:::rti
"rti"
*mn10300

*am33
*am33_2

{
  /* OP_F0FD (); */
  unsigned32 sp;

  sp = State.regs[REG_SP];
  PSW = load_half(sp);
  State.regs[REG_PC] = load_word(sp+4);
  State.regs[REG_SP] +=8;
  nia = PC;
}


// 1111 0000 1111 1110; trap
8.0xf0+8.0xfe:D0:::trap
"trap"
*mn10300

*am33
*am33_2

{
  /* OP_F0FE (); */
  unsigned32 sp, next_pc;

  PC = cia;
  sp = State.regs[REG_SP];
  next_pc = State.regs[REG_PC] + 2;
  store_word(sp, next_pc);
  nia = PC;
}


// 1111 0000 1111 1111; rtm
8.0xf0+8.0xff:D0:::rtm
"rtm"
*mn10300

*am33
*am33_2

{
  /* OP_F0FF (); */
  PC = cia;
  abort ();
}


// 1100 1011; nop
8.0xcb:S0:::nop
"nop"
*mn10300

*am33
*am33_2

{
  /* OP_CB (); */
  PC = cia;
}


// 1111 0101 0000  DmDn; udf20 Dm,Dn
8.0xf5+4.0x0,2.DM1,2.DN0:D0:::putx
"putx"
*mn10300
{
  /* OP_F500 (); */
  PC = cia;
  State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
}


// 1111 0110 1111 DmDn; udf15 Dm,Dn
8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
"getx"
*mn10300

*am33
*am33_2

{
  /* OP_F6F0 (); */
  int z, n;

  PC = cia;
  z = (State.regs[REG_MDRQ] == 0);
  n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
  State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
}


// 1111 0110 0000 DmDn; udf00 Dm,Dn
8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
"mulq"
*mn10300

*am33
*am33_2

{
  /* OP_F600 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
          *  (signed64)(signed32)State.regs[REG_D0 + DM1]);
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
"mulq"
*mn10300

*am33
*am33_2

{
  /* OP_F90000 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
          * (signed64)(signed32)EXTEND8 (IMM8));
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
"mulq"
*mn10300

*am33
*am33_2

{
  /* OP_FB000000 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
          * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
"mulq"
*mn10300

*am33
*am33_2

{
  /* OP_FD000000 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
          * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 0110 0001 DmDn; udf01 Dm,Dn
8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
"mulqu"
*mn10300

*am33
*am33_2

{
  /* OP_F610 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((unsigned64) State.regs[REG_D0 + DN0]
	  * (unsigned64) State.regs[REG_D0 + DM1]);
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
"mulqu"
*mn10300

*am33
*am33_2

{
  /* OP_F91400 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((unsigned64)State.regs[REG_D0 + DN0]
	  * (unsigned64)EXTEND8 (IMM8));
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
"mulqu"
*mn10300

*am33
*am33_2

{
  /* OP_FB140000 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((unsigned64)State.regs[REG_D0 + DN0]
	  * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
"mulqu"
*mn10300

*am33
*am33_2

{
  /* OP_FD140000 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((unsigned64)State.regs[REG_D0 + DN0]
          * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 0110 0100 DmDn; udf04 Dm,Dn
8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
"sat16"
*mn10300

*am33
*am33_2

{
  /* OP_F640 (); */
  int temp;

  PC = cia;
  temp = State.regs[REG_D0 + DM1];