mn10300.igen

这个是LINUX下的GDB调度工具的源码

  PC = cia;
  State.regs[REG_D0 + DN0]
    &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
"and"
*mn10300

*am33
*am33_2

{
  /* OP_FAFC0000 (); */
  PC = cia;
  PSW &= FETCH16(IMM16A, IMM16B);
}



// 1111 0010 0001 DmDn; or DmDn
8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
"or"
*mn10300

*am33
*am33_2

{
  /* OP_F210 (); */
  PC = cia;
  genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
}


// 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
"or"
*mn10300

*am33
*am33_2

{
  /* OP_F8E400 (); */
  PC = cia;
  genericOr(IMM8, REG_D0 + DN0);
}


// 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
"or"
*mn10300

*am33
*am33_2

{
  /* OP_FAE40000 (); */
  PC = cia;
  genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
}


// 1111 1100 1110 01Dn imm32...; or imm32,Dn
8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
"or"
*mn10300

*am33
*am33_2

{
  /* OP_FCE40000 (); */
  PC = cia;
  genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
}


// 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
"or"
*mn10300

*am33
*am33_2

{
  /* OP_FAFD0000 (); */
  PC = cia;
  PSW |= FETCH16(IMM16A, IMM16B);
}


// 1111 0010 0010 DmDn; xor Dm,Dn
8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
"xor"
*mn10300

*am33
*am33_2

{
  /* OP_F220 (); */
  PC = cia;
  genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
}


// 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
"xor"
*mn10300

*am33
*am33_2

{
  /* OP_FAE80000 (); */
  PC = cia;
  genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
}


// 1111 1100 1110 10Dn imm32...; xor imm32,Dn
8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
"xor"
*mn10300

*am33
*am33_2

{
  /* OP_FCE80000 (); */
  PC = cia;
  genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
}


// 1111 0010 0011 00Dn; not Dn
8.0xf2+4.0x3,00,2.DN0:D0:::not
"not"
*mn10300

*am33
*am33_2

{
  /* OP_F230 (); */
  int n, z;

  PC = cia;
  State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
"btst"
*mn10300

*am33
*am33_2

{
  /* OP_F8EC00 (); */
  PC = cia;
  genericBtst(IMM8, State.regs[REG_D0 + DN0]);
}


// 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
"btst"
*mn10300

*am33
*am33_2

{
  /* OP_FAEC0000 (); */
  PC = cia;
  genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
}


// 1111 1100 1110 11Dn imm32...; btst imm32,Dn
8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
"btst"
*mn10300

*am33
*am33_2

{
  /* OP_FCEC0000 (); */
  PC = cia;
  genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
	      State.regs[REG_D0 + DN0]);
}


// 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
"btst"
*mn10300

*am33
*am33_2

{
  /* OP_FE020000 (); */
  PC = cia;
  genericBtst(IMM8,
	      load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
}


// 1111 1010 1111 10An d8...... imm8....; 
// btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
"btst"
*mn10300

*am33
*am33_2

{
  /* OP_FAF80000 (); */
  PC = cia;
  genericBtst(IMM8,
	      load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
}


// 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
"bset"
*mn10300

*am33
*am33_2

{
  /* OP_F080 (); */
  unsigned32 temp;
  int z;

  PC = cia;
  temp = load_byte (State.regs[REG_A0 + AN0]);
  z = (temp & State.regs[REG_D0 + DM1]) == 0;
  temp |= State.regs[REG_D0 + DM1];
  store_byte (State.regs[REG_A0 + AN0], temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}


// 1111 1110 0000 0000 abs32... imm8....;
// bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
"bset"
*mn10300

*am33
*am33_2

{
  /* OP_FE000000 (); */
  unsigned32 temp;
  int z;

  PC = cia;
  temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
  z = (temp & IMM8) == 0;
  temp |= IMM8;
  store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}


// 1111 1010 1111 00AnAn d8...... imm8....;
// bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
"bset"
*mn10300

*am33
*am33_2

{
  /* OP_FAF00000 (); */
  unsigned32 temp;
  int z;

  PC = cia;
  temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
  z = (temp & (IMM8)) == 0;
  temp |= (IMM8);
  store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}


// 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
"bclr"
*mn10300

*am33
*am33_2

{
  /* OP_F090 (); */
  unsigned32 temp;
  int z;

  PC = cia;
  temp = load_byte (State.regs[REG_A0 + AN0]);
  z = (temp & State.regs[REG_D0 + DM1]) == 0;
  temp = temp & ~State.regs[REG_D0 + DM1];
  store_byte (State.regs[REG_A0 + AN0], temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}


// 1111 1110 0000 0001 abs32... imm8....;
// bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
"bclr"
*mn10300

*am33
*am33_2

{
  /* OP_FE010000 (); */
  unsigned32 temp;
  int z;

  PC = cia;
  temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
  z = (temp & IMM8) == 0;
  temp = temp & ~(IMM8);
  store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}


// 1111 1010 1111 01An d8...... imm8....;
// bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
"bclr"
*mn10300

*am33
*am33_2

{
  /* OP_FAF40000 (); */
  unsigned32 temp;
  int z;

  PC = cia;
  temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
  z = (temp & (IMM8)) == 0;
  temp = temp & ~(IMM8);
  store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}


// 1111 0010 1011 DmDn; asr Dm,Dn
8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
"asr"
*mn10300

*am33
*am33_2

{
  /* OP_F2B0 (); */
  signed32 temp;
  int z, n, c;

  PC = cia;
  temp = State.regs[REG_D0 + DN0];
  c = temp & 1;
  temp >>= State.regs[REG_D0 + DM1];
  State.regs[REG_D0 + DN0] = temp;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}


// 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
"asr"
*mn10300

*am33
*am33_2

{
  /* OP_F8C800 (); */
  signed32 temp;
  int z, n, c;

  PC = cia;
  temp = State.regs[REG_D0 + DN0];
  c = temp & 1;
  temp >>= IMM8;
  State.regs[REG_D0 + DN0] = temp;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}


// 1111 0010 1010 DmDn; lsr Dm,Dn
8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
"lsr"
*mn10300

*am33
*am33_2

{
  /* OP_F2A0 (); */
  int z, n, c;

  PC = cia;
  c = State.regs[REG_D0 + DN0] & 1;
  State.regs[REG_D0 + DN0]
    >>= State.regs[REG_D0 + DM1];
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}


// 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
"lsr"
*mn10300

*am33
*am33_2

{
  /* OP_F8C400 (); */
  int z, n, c;

  PC = cia;
  c = State.regs[REG_D0 + DN0] & 1;
  State.regs[REG_D0 + DN0] >>=  IMM8;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}


// 1111 0010 1001 DmDn; asl Dm,Dn
8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
"asl"
*mn10300

*am33
*am33_2

{
  /* OP_F290 (); */
  int n, z;

  PC = cia;
  State.regs[REG_D0 + DN0]
    <<= State.regs[REG_D0 + DM1];
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
"asl"
*mn10300

*am33
*am33_2

{
  /* OP_F8C000 (); */
  int n, z;

  PC = cia;
  State.regs[REG_D0 + DN0] <<= IMM8;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 0101 01Dn; als2 Dn
4.0x5,01,2.DN0:S0:::asl2
"asl2"
*mn10300

*am33
*am33_2

{
  /* OP_54 (); */
  int n, z;
  PC = cia;

  State.regs[REG_D0 + DN0] <<= 2;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 0010 1000 01Dn; ror Dn
8.0xf2+4.0x8,01,2.DN0:D0:::ror
"ror"
*mn10300

*am33
*am33_2

{
  /* OP_F284 (); */
  unsigned32 value;
  int c,n,z;

  PC = cia;
  value = State.regs[REG_D0 + DN0];
  c = (value & 0x1);

  value >>= 1;
  value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
  State.regs[REG_D0 + DN0] = value;
  z = (value == 0);
  n = (value & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}


// 1111 0010 1000 00Dn; rol Dn
8.0xf2+4.0x8,00,2.DN0:D0:::rol
"rol"
*mn10300

*am33
*am33_2

{
  /* OP_F280 (); */
  unsigned32 value;
  int c,n,z;

  PC = cia;
  value = State.regs[REG_D0 + DN0];
  c = (value & 0x80000000) ? 1 : 0;

  value <<= 1;
  value |= ((PSW & PSW_C) != 0);
  State.regs[REG_D0 + DN0] = value;
  z = (value == 0);
  n = (value & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}


// 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
8.0xc8+8.D8:S1:::beq
"beq"
*mn10300

*am33
*am33_2

{
  /* OP_C800 (); */
  PC = cia;
  if ((PSW & PSW_Z))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
8.0xc9+8.D8:S1:::bne
"bne"
*mn10300

*am33
*am33_2

{
  /* OP_C900 (); */
  PC = cia;
  if (!(PSW & PSW_Z))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
8.0xc1+8.D8:S1:::bgt
"bgt"
*mn10300

*am33
*am33_2

{
  /* OP_C100 (); */
  PC = cia;
  if (!((PSW & PSW_Z)
        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
8.0xc2+8.D8:S1:::bge
"bge"
*mn10300

*am33
*am33_2

{
  /* OP_C200 (); */
  PC = cia;
  if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
8.0xc3+8.D8:S1:::ble
"ble"
*mn10300

*am33
*am33_2

{
  /* OP_C300 (); */
  PC = cia;
  if ((PSW & PSW_Z)
      || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
8.0xc0+8.D8:S1:::blt
"blt"
*mn10300

*am33
*am33_2

{
  /* OP_C000 (); */
  PC = cia;
  if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
8.0xc5+8.D8:S1:::bhi
"bhi"
*mn10300

*am33
*am33_2

{
  /* OP_C500 (); */
  PC = cia;
  if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
8.0xc6+8.D8:S1:::bcc
"bcc"
*mn10300

*am33
*am33_2

{
  /* OP_C600 (); */
  PC = cia;
  if (!(PSW & PSW_C))
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
8.0xc7+8.D8:S1:::bls
"bls"
*mn10300

*am33
*am33_2

{
  /* OP_C700 (); */
  PC = cia;
  if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
    {
      State.regs[REG_PC] += EXTEND8 (D8);
      nia = PC;
    }
}


// 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
8.0xc4+8.D8:S1:::bcs
"bcs"
*mn10300