mn10300.igen

这个是LINUX下的GDB调度工具的源码

// 0000 Dn00; clr Dn
4.0x0,2.DN1,00:S0:::clr
"clr"
*mn10300

*am33
*am33_2

{
  /* OP_0 (); */
  PC = cia;
  State.regs[REG_D0 + DN1] = 0;

  PSW |= PSW_Z;
  PSW &= ~(PSW_V | PSW_C | PSW_N);
}


// 1110 DmDn; add Dm,Dn
4.0xe,2.DM1,2.DN0:S0:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_E0 (); */
  PC = cia;
  genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
}

// 1111 0001 0110 DmAn; add Dm,An
8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_F160 (); */
  PC = cia;
  genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
}


// 1111 0001 0101 AmDn; add Am,Dn
8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_F150 (); */
  PC = cia;
  genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
}


// 1111 0001 0111 AmAn; add Am,An
8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_F170 (); */
  PC = cia;
  genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
}


// 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
4.0x2,10,2.DN0+8.IMM8:S1:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_2800 (); */
  PC = cia;
  genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
}


// 1111 1010 1100 00Dn imm16...; add imm16,Dn
8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_FAC00000 (); */
  PC = cia;
  genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
}


// 1111 1100 1100 00Dn imm32...; add imm32,Dn
8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_FCC00000 (); */
  PC = cia;
  genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
}


// 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
4.0x2,00,2.AN0+8.IMM8:S1a:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_2000 (); */
  PC = cia;
  genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
}


// 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_FAD00000 (); */
  PC = cia;
  genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
}


// 1111 1100 1101 00An imm32...; add imm32,An
8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_FCD00000 (); */
  PC = cia;
  genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
}


// 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
8.0xf8+8.0xfe+8.IMM8:D1:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_F8FE00 (); */
  unsigned32 imm;

  /* Note: no PSW changes. */
  PC = cia;
  imm = EXTEND8 (IMM8);
  State.regs[REG_SP] += imm;
}


// 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_FAFE0000 (); */
  unsigned32 imm;

  /* Note: no PSW changes. */
  PC = cia;
  imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
  State.regs[REG_SP] += imm;
}


// 1111 1100 1111 1110 imm32...; add imm32,SP
8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
"add"
*mn10300

*am33
*am33_2

{
  /* OP_FCFE0000 (); */
  unsigned32 imm;

  /* Note: no PSW changes. */
  PC = cia;
  imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
  State.regs[REG_SP] += imm;
}


// 1111 0001 0100 DmDn; addc Dm,Dn
8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
"addc"
*mn10300

*am33
*am33_2

{
  /* OP_F140 (); */
  int z, c, n, v;
  unsigned32 reg1, reg2, sum;

  PC = cia;
  reg1 = State.regs[REG_D0 + DM1];
  reg2 = State.regs[REG_D0 + DN0];
  sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
  State.regs[REG_D0 + DN0] = sum;

  z = ((PSW & PSW_Z) != 0) && (sum == 0);
  n = (sum & 0x80000000);
  c = (sum < reg1) || (sum < reg2);
  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
       && (reg2 & 0x80000000) != (sum & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
	  | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}


// 1111 0001 0000 DmDn; sub Dm,Dn
8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
"sub"
*mn10300

*am33
*am33_2

{
  /* OP_F100 (); */
  PC = cia;
  genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
}

// 1111 0001 0010 DmAn; sub DmAn
8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
"sub"
*mn10300

*am33
*am33_2

{
  /* OP_F120 (); */
  PC = cia;
  genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
}


// 1111 0001 0001 AmDn; sub AmDn
8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
"sub"
*mn10300

*am33
*am33_2

{
  /* OP_F110 (); */
  PC = cia;
  genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
}


// 1111 0001 0011 AmAn; sub Am,An
8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
"sub"
*mn10300

*am33
*am33_2

{
  /* OP_F130 (); */
  PC = cia;
  genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
}


// 1111 1100 1100 01Dn imm32...; sub imm32,Dn
8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
"sub"
*mn10300

*am33
*am33_2

{
  /* OP_FCC40000 (); */
  PC = cia;
  genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
}


// 1111 1100 1101 01An imm32...; sub imm32,An
8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
"sub"
*mn10300

*am33
*am33_2

{
  /* OP_FCD40000 (); */
  PC = cia;
  genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
}


// 1111 0001 1000 DmDn; subc Dm,Dn
8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
"subc"
*mn10300

*am33
*am33_2

{
  /* OP_F180 (); */
  int z, c, n, v;
  unsigned32 reg1, reg2, difference;

  PC = cia;
  reg1 = State.regs[REG_D0 + DM1];
  reg2 = State.regs[REG_D0 + DN0];
  difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
  State.regs[REG_D0 + DN0] = difference;

  z = ((PSW & PSW_Z) != 0) && (difference == 0);
  n = (difference & 0x80000000);
  c = (reg1 > reg2);
  v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
       && (reg2 & 0x80000000) != (difference & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
	  | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}


// 1111 0010 0100 DmDn; mul Dm,Dn
8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
"mul"
*mn10300

*am33
*am33_2

{
  /* OP_F240 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
          *  (signed64)(signed32)State.regs[REG_D0 + DM1]);
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 0010 0101 DmDn; mulu Dm,Dn
8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
"mulu"
*mn10300

*am33
*am33_2

{
  /* OP_F250 (); */
  unsigned64 temp;
  int n, z;

  PC = cia;
  temp = ((unsigned64)State.regs[REG_D0 + DN0]
          * (unsigned64)State.regs[REG_D0 + DM1]);
  State.regs[REG_D0 + DN0] = temp & 0xffffffff;
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 0010 0110 DmDn; div Dm,Dn
8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
"div"
*mn10300

*am33
*am33_2

{
  /* OP_F260 (); */
  signed64 temp;
  signed32 denom;
  int n, z, v;

  PC = cia;
  denom = (signed32)State.regs[REG_D0 + DM1];

  temp = State.regs[REG_MDR];
  temp <<= 32;
  temp |= State.regs[REG_D0 + DN0];
  if ( !(v = (0 == denom)) )
    {
      State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
      temp /= (signed32)State.regs[REG_D0 + DM1];
      State.regs[REG_D0 + DN0] = temp & 0xffffffff;
    }
  else
    {
      State.regs[REG_MDR] = temp;
      State.regs[REG_D0 + DN0] = 0xff;
    }
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
}


// 1111 0010 0111 DmDn; divu Dm,Dn
8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
"divu"
*mn10300

*am33
*am33_2

{
  /* OP_F270 (); */
  unsigned64 temp;
  unsigned32 denom;
  int n, z, v;

  PC = cia;
  denom = (unsigned32)State.regs[REG_D0 + DM1];
  temp = State.regs[REG_MDR];
  temp <<= 32;
  temp |= State.regs[REG_D0 + DN0];
  if ( !(v = (0 == denom)) ) 
    {
      State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
      temp /= State.regs[REG_D0 + DM1];
      State.regs[REG_D0 + DN0] = temp & 0xffffffff;
    }
  else
    {
      State.regs[REG_MDR] = temp;
      State.regs[REG_D0 + DN0] = 0xff;
    }
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
}


// 0100 Dn00; inc Dn
4.0x4,2.DN1,00:S0:::inc
"inc"
*mn10300

*am33
*am33_2

{
  /* OP_40 (); */
  unsigned32 imm;

  PC = cia;
  imm = 1;
  genericAdd(imm, REG_D0 + DN1);
}


// 0100 An01
4.0x4,2.AN1,01:S0a:::inc
"inc"
*mn10300

*am33
*am33_2

{
  /* OP_41 (); */
  PC = cia;
  State.regs[REG_A0 + AN1] += 1;
}


// 0101 00An; inc4 An
4.0x5,00,2.AN0:S0:::inc4
"inc4"
*mn10300

*am33
*am33_2

{
  /* OP_50 (); */
  PC = cia;
  State.regs[REG_A0 + AN0] += 4;
}


// 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  PC = cia;
  /* OP_A000 (); */
  genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
}


// 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  PC = cia;
  /* OP_A0 (); */
  genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
}


// 1111 0001 1010 DmAn; cmp Dm,An
8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  /* OP_F1A0 (); */
  PC = cia;
  genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
}


// 1111 0001 1001 AmDn; cmp Am,Dn
8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  /* OP_F190 (); */
  PC = cia;
  genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
}


// 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  PC = cia;
  /* OP_B000 (); */
  genericCmp(IMM8,
	     State.regs[REG_A0 + AN0]);
}


// 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  PC = cia;
  /* OP_B0 (); */
  genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
}


// 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  /* OP_FAC80000 (); */
  PC = cia;
  genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
	     State.regs[REG_D0 + DN0]);
}


// 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  /* OP_FCC80000 (); */
  PC = cia;
  genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
	     State.regs[REG_D0 + DN0]);
}


// 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  /* OP_FAD80000 (); */
  PC = cia;
  genericCmp(FETCH16(IMM16A, IMM16B),
	     State.regs[REG_A0 + AN0]);
}


// 1111 1100 1101 10An imm32...; cmp imm32,An
8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
"cmp"
*mn10300

*am33
*am33_2

{
  /* OP_FCD80000 (); */
  PC = cia;
  genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
	     State.regs[REG_A0 + AN0]);
}


// 1111 0010 0000 DmDn; and Dm,Dn
8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
"and"
*mn10300

*am33
*am33_2

{
  /* OP_F200 (); */
  int n, z;

  PC = cia;
  State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
"and"
*mn10300

*am33
*am33_2

{
  /* OP_F8E000 (); */
  int n, z;

  PC = cia;
  State.regs[REG_D0 + DN0] &= IMM8;
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
"and"
*mn10300

*am33
*am33_2

{
  /* OP_FAE00000 (); */
  int n, z;

  PC = cia;
  State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
  z = (State.regs[REG_D0 + DN0] == 0);
  n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1100 1110 00Dn imm32...; and imm32,Dn
8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
"and"
*mn10300

*am33
*am33_2

{
  /* OP_FCE00000 (); */
  int n, z;