am33.igen

这个是LINUX下的GDB调度工具的源码

  /* 16bit saturation */
  else if (IMM8 == 0x10)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x7fff)    
	State.regs[dstreg] = 0x7fff;
      else if (tmp < 0xffffffffffff8000LL)
	State.regs[dstreg] = 0x8000;
      else
	State.regs[dstreg] = tmp;
    }
  /* 8 bit saturation */
  else if (IMM8 == 0x8)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x7f)    
	State.regs[dstreg] = 0x7f;
      else if (tmp < 0xffffffffffffff80LL)
	State.regs[dstreg] = 0x80;
      else
	State.regs[dstreg] = tmp;
    }
  /* 9 bit saturation */
  else if (IMM8 == 0x9)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x80)    
	State.regs[dstreg] = 0x80;
      else if (tmp < 0xffffffffffffff81LL)
	State.regs[dstreg] = 0x81;
      else
	State.regs[dstreg] = tmp;
    }
  /* 9 bit saturation */
  else if (IMM8 == 0x30)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x7fffffffffffLL)    
	tmp = 0x7fffffffffffLL;
      else if (tmp < 0xffff800000000000LL)
	tmp = 0xffff800000000000LL;

      tmp >>= 16;
      State.regs[dstreg] = tmp;
    }
}

// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
"add"
*am33
*am33_2
{
  int z, c, n, v;
  unsigned32 sum, source1, source2;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  source1 = State.regs[srcreg1];
  source2 = State.regs[srcreg2];
  sum = source1 + source2;
  State.regs[dstreg] = sum;

  z = (sum == 0);
  n = (sum & 0x80000000);
  c = (sum < source1) || (sum < source2);
  v = ((source1 & 0x80000000) == (source2 & 0x80000000)
       && (source1 & 0x80000000) != (sum & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
"addc"
*am33
*am33_2
{
  int z, c, n, v;
  unsigned32 sum, source1, source2;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  source1 = State.regs[srcreg1];
  source2 = State.regs[srcreg2];
  sum = source1 + source2 + ((PSW & PSW_C) != 0);
  State.regs[dstreg] = sum;

  z = ((PSW & PSW_Z) != 0) && (sum == 0);
  n = (sum & 0x80000000);
  c = (sum < source1) || (sum < source2);
  v = ((source1 & 0x80000000) == (source2 & 0x80000000)
       && (source1 & 0x80000000) != (sum & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
"sub"
*am33
*am33_2
{
  int z, c, n, v;
  unsigned32 difference, source1, source2;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  source1 = State.regs[srcreg1];
  source2 = State.regs[srcreg2];
  difference = source2 - source1;
  State.regs[dstreg] = difference;

  z = (difference == 0);
  n = (difference & 0x80000000);
  c = (source1 > source1);
  v = ((source1 & 0x80000000) == (source2 & 0x80000000)
       && (source1 & 0x80000000) != (difference & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
"subc"
*am33
*am33_2
{
  int z, c, n, v;
  unsigned32 difference, source1, source2;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  source1 = State.regs[srcreg1];
  source2 = State.regs[srcreg2];
  difference = source2 - source1 - ((PSW & PSW_C) != 0);
  State.regs[dstreg] = difference;

  z = ((PSW & PSW_Z) != 0) && (difference == 0);
  n = (difference & 0x80000000);
  c = (source1 > source2);
  v = ((source1 & 0x80000000) == (source2 & 0x80000000)
       && (source1 & 0x80000000) != (difference & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
"and"
*am33
*am33_2
{
  int z, n;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];

  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000);

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
}

// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
"or"
*am33
*am33_2
{
  int z, n;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];

  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000);

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
}

// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
"xor"
*am33
*am33_2
{
  int z, n;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];

  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000);

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
}

// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
"asr"
*am33
*am33_2
{
  int z, c, n;
  signed32 temp;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  temp = State.regs[srcreg2];
  c = temp & 1;
  temp >>= State.regs[srcreg1];
  State.regs[dstreg] = temp;

  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000);

  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
}

// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
"lsr"
*am33
*am33_2
{
  int z, c, n;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  c = State.regs[srcreg2] & 1;
  State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];

  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000);

  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
}

// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
"asl"
*am33
*am33_2
{
  int z, n;
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg = translate_rreg (SD_, RD0);

  State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];

  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000);

  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
}

// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
"mul"
*am33
*am33_2
{
  int srcreg1, srcreg2, dstreg1, dstreg2;
  signed64 temp;
  int n, z;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg1 = translate_rreg (SD_, RD0);
  dstreg2 = translate_rreg (SD_, RD2);

  temp = ((signed64)(signed32)State.regs[srcreg1]
          *  (signed64)(signed32)State.regs[srcreg2]);
  State.regs[dstreg2] = temp & 0xffffffff;
  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;

  z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
  n = (State.regs[dstreg1] & 0x80000000);

  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
}

// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
"mulu"
*am33
*am33_2
{
  int srcreg1, srcreg2, dstreg1, dstreg2;
  signed64 temp;
  int n, z;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg1 = translate_rreg (SD_, RD0);
  dstreg2 = translate_rreg (SD_, RD2);

  temp = ((unsigned64)State.regs[srcreg1]
          *  (unsigned64)State.regs[srcreg2]);
  State.regs[dstreg2] = temp & 0xffffffff;
  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;

  z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
  n = (State.regs[dstreg1] & 0x80000000);

  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
}

// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
"mov"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_word (IMM8);
}

// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
"mov"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_word (IMM8, State.regs[srcreg]);
}

// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
"movbu"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_byte (IMM8);
}

// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_byte (IMM8, State.regs[srcreg]);
}

// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
"movhu"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_half (IMM8);
}

// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_half (IMM8, State.regs[srcreg]);
}

// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
"mov"
*am33
*am33_2
{
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM0);
  srcreg2 = translate_rreg (SD_, RI0);
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
}

// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg1, dstreg2;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg1 = translate_rreg (SD_, RI0);
  dstreg2 = translate_rreg (SD_, RN0);
  store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
}

// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM0);
  srcreg2 = translate_rreg (SD_, RI0);
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
}

// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg, dstreg1, dstreg2;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg1 = translate_rreg (SD_, RI0);
  dstreg2 = translate_rreg (SD_, RN0);
  store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
}

// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg1, srcreg2, dstreg;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM0);
  srcreg2 = translate_rreg (SD_, RI0);
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
}

// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg1, dstreg2;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg1 = translate_rreg (SD_, RI0);
  dstreg2 = translate_rreg (SD_, RN0);
  store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
}

// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
"mac"
*am33
*am33_2
{
  int srcreg1, srcreg2, dstreg1, dstreg2;
  signed64 temp;
  unsigned32 sum;
  int c, v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);
  dstreg1 = translate_rreg (SD_, RD0);
  dstreg2 = translate_rreg (SD_, RD2);

  temp = ((signed64)(signed32)State.regs[srcreg1]
          *  (signed64)(signed32)State.regs[srcreg2]);

  sum = State.regs[dstreg2] + (temp & 0xffffffff);
  c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
  State.regs[dstreg2] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[dstreg1] + temp + c;
  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[dstreg1] = sum;
  if (v)
    {
      State.regs[REG_MCVF] = 1;
      PSW &= ~(PSW_V);
      PSW |= (( v ? PSW_V : 0));
    }
}

// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
"macu"
*am33
*am33_2
{
  int srcreg1,