am33.igen

这个是LINUX下的GDB调度工具的源码

  PC = cia;
  dstreg = translate_xreg (SD_, XRN0);

  State.regs[dstreg] = IMM8;
}

// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
"and"
*am33
*am33_2
{
  int dstreg;
  int z, n;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] &= (IMM8 & 0xff);
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
"or"
*am33
*am33_2
{
  int dstreg;
  int z, n;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] |= (IMM8 & 0xff);
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
"xor"
*am33
*am33_2
{
  int dstreg;
  int z, n;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] ^= (IMM8 & 0xff);
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
"asr"
*am33
*am33_2
{
  int dstreg;
  signed32 temp;
  int c, z, n;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  temp = State.regs[dstreg];
  c = temp & 1;
  temp >>= (IMM8 & 0xff);
  State.regs[dstreg] = temp;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
"lsr"
*am33
*am33_2
{
  int dstreg;
  int z, n, c;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  c = State.regs[dstreg] & 1;
  State.regs[dstreg] >>= (IMM8 & 0xff);
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
"asl"
*am33
*am33_2
{
  int dstreg;
  int z, n;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] <<= (IMM8 & 0xff);
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
"mul"
*am33
*am33_2
{
  int dstreg;
  unsigned64 temp;
  int z, n;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  temp = ((signed64)(signed32)State.regs[dstreg]
          *  (signed64)(signed32)EXTEND8 (IMM8));
  State.regs[dstreg] = temp & 0xffffffff;
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
"mulu"
*am33
*am33_2
{
  int dstreg;
  unsigned64 temp;
  int z, n;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  temp = ((unsigned64)State.regs[dstreg]
          * (unsigned64)(IMM8 & 0xff));
  State.regs[dstreg] = temp & 0xffffffff;
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
"btst"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  genericBtst(IMM8, State.regs[srcreg]);
}

// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
}

// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
}

// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
}

// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
}

// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
}

// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
}

// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_word (State.regs[srcreg]);
  State.regs[srcreg] += EXTEND8 (IMM8);
}

// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_word (State.regs[dstreg], State.regs[srcreg]);
  State.regs[dstreg] += EXTEND8 (IMM8);
}


// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
"mov"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
}

// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
"mov"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
}

// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
"movbu"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
}

// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
}

// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
"movhu"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
}

// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
}

// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_half (State.regs[srcreg]);
  State.regs[srcreg] += EXTEND8 (IMM8);
}

// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_half (State.regs[dstreg], State.regs[srcreg]);
  State.regs[dstreg] += EXTEND8 (IMM8);
}


// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
"mac"
*am33
*am33_2
{
  int srcreg;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg = translate_rreg (SD_, RN2);

  temp = ((signed64)(signed32)EXTEND8 (IMM8)
          * (signed64)(signed32)State.regs[srcreg]);
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
"macu"
*am33
*am33_2
{
  int srcreg;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg = translate_rreg (SD_, RN2);

  temp = ((unsigned64) (IMM8)
          * (unsigned64)State.regs[srcreg]);
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
"macb"
*am33
*am33_2
{
  int srcreg;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg = translate_rreg (SD_, RN2);

  temp = ((signed64)(signed8)EXTEND8 (IMM8)
          * (signed64)(signed8)State.regs[srcreg] & 0xff);
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
"macbu"
*am33
*am33_2
{
  int srcreg;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg = translate_rreg (SD_, RN2);

  temp = ((unsigned64) (IMM8)
          * (unsigned64)State.regs[srcreg] & 0xff);
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
"mach"
*am33
*am33_2
{
  int srcreg;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg = translate_rreg (SD_, RN2);

  temp = ((signed64)(signed16)EXTEND8 (IMM8)
          * (signed64)(signed16)State.regs[srcreg] & 0xffff);
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
"machu"
*am33
*am33_2
{
  int srcreg;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg = translate_rreg (SD_, RN2);

  temp = ((unsigned64) (IMM8)
          * (unsigned64)State.regs[srcreg] & 0xffff);
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
"mcste"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  PSW &= ~(PSW_V | PSW_C);
  PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
  
  /* 32bit saturation.  */
  if (IMM8 == 0x20)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x7fffffff)    
	State.regs[dstreg] = 0x7fffffff;
      else if (tmp < 0xffffffff80000000LL)
	State.regs[dstreg] = 0x80000000;
      else
	State.regs[dstreg] = tmp;
    }