am33.igen

这个是LINUX下的GDB调度工具的源码

"mac"
*am33
*am33_2
{
  int srcreg1, srcreg2;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);

  temp = ((signed64)(signed32)State.regs[srcreg2]
          * (signed64)(signed32)State.regs[srcreg1]);
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
"macu"
*am33
*am33_2
{
  int srcreg1, srcreg2;
  unsigned64 temp, sum;
  int c, v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);

  temp = ((unsigned64)State.regs[srcreg2]
          * (unsigned64)State.regs[srcreg1]);
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
"macb"
*am33
*am33_2
{
  int srcreg1, srcreg2;
  signed32 temp, sum;
  int v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);

  temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
          * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
  sum = State.regs[REG_MCRL] + temp;
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRL] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
"macbu"
*am33
*am33_2
{
  int srcreg1, srcreg2;
  signed64 temp, sum;
  int v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);

  temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
          * (unsigned32)(State.regs[srcreg1] & 0xff));
  sum = State.regs[REG_MCRL] + temp;
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRL] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
"mach"
*am33
*am33_2
{
  int srcreg1, srcreg2;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);

  temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
          * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
"machu"
*am33
*am33_2
{
  int srcreg1, srcreg2;
  signed64 temp, sum;
  int c, v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);

  temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
          * (unsigned64)(State.regs[srcreg1] & 0xffff));
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
  State.regs[REG_MCRL] = sum;
  temp >>= 32;
  temp &= 0xffffffff;
  sum = State.regs[REG_MCRH] + temp + c;
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRH] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
"dmach"
*am33
*am33_2
{
  int srcreg1, srcreg2;
  signed32 temp, temp2, sum;
  int v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);

  temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
	   * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
  sum = temp + temp2 + State.regs[REG_MCRL];
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRL] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
"dmachu"
*am33
*am33_2
{
  int srcreg1, srcreg2;
  unsigned32 temp, temp2, sum;
  int v;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RM2);
  srcreg2 = translate_rreg (SD_, RN0);

  temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
          * (unsigned32)(State.regs[srcreg1] & 0xffff));
  temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
	   * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
  sum = temp + temp2 + State.regs[REG_MCRL];
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
        && (temp & 0x80000000) != (sum & 0x80000000));
  State.regs[REG_MCRL] = sum;
  if (v)
    State.regs[REG_MCVF] = 1;
}

// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
"dmulh"
*am33
*am33_2
{
  int srcreg, dstreg;
  signed32 temp;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
          * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
  State.regs[REG_MDRQ] = temp;
  temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
          * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
  State.regs[dstreg] = temp;
}

// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
"dmachu"
*am33
*am33_2
{
  int srcreg, dstreg;
  unsigned32 temp;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
          * (unsigned32)(State.regs[srcreg] & 0xffff));
  State.regs[REG_MDRQ] = temp;
  temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
          * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
  State.regs[dstreg] = temp;
}

// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
"sat16"
*am33
*am33_2
{
  int srcreg, dstreg;
  int value, z, n;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  value = State.regs[srcreg];

  if (value >= 0x7fff)
    State.regs[dstreg] = 0x7fff;
  else if (value <= 0xffff8000)
    State.regs[dstreg] = 0xffff8000;
  else
    State.regs[dstreg] = value;

  n = (State.regs[dstreg] & 0x8000) != 0;
  z = (State.regs[dstreg] == 0);
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn 
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
"mcste"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  PSW &= ~(PSW_V | PSW_C);
  PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
  
  /* 32bit saturation.  */
  if (State.regs[srcreg] == 0x20)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x7fffffff)    
	State.regs[dstreg] = 0x7fffffff;
      else if (tmp < 0xffffffff80000000LL)
	State.regs[dstreg] = 0x80000000;
      else
	State.regs[dstreg] = tmp;
    }
  /* 16bit saturation */
  else if (State.regs[srcreg] == 0x10)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x7fff)    
	State.regs[dstreg] = 0x7fff;
      else if (tmp < 0xffffffffffff8000LL)
	State.regs[dstreg] = 0x8000;
      else
	State.regs[dstreg] = tmp;
    }
  /* 8 bit saturation */
  else if (State.regs[srcreg] == 0x8)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x7f)    
	State.regs[dstreg] = 0x7f;
      else if (tmp < 0xffffffffffffff80LL)
	State.regs[dstreg] = 0x80;
      else
	State.regs[dstreg] = tmp;
    }
  /* 9 bit saturation */
  else if (State.regs[srcreg] == 0x9)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x80)    
	State.regs[dstreg] = 0x80;
      else if (tmp < 0xffffffffffffff81LL)
	State.regs[dstreg] = 0x81;
      else
	State.regs[dstreg] = tmp;
    }
  /* 9 bit saturation */
  else if (State.regs[srcreg] == 0x30)
    {
      signed64 tmp;

      tmp = State.regs[REG_MCRH];
      tmp <<= 32;
      tmp += State.regs[REG_MCRL];

      if (tmp > 0x7fffffffffffLL)    
	tmp = 0x7fffffffffffLL;
      else if (tmp < 0xffff800000000000LL)
	tmp = 0xffff800000000000LL;

      tmp >>= 16;
      State.regs[dstreg] = tmp;
    }
}

// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
"swap"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
			| (((State.regs[srcreg] >> 8) & 0xff) << 16)
			| (((State.regs[srcreg] >> 16) & 0xff) << 8)
			| ((State.regs[srcreg] >> 24) & 0xff));
}

// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
"swaph"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
			| ((State.regs[srcreg] >> 8) & 0xff)
			| (((State.regs[srcreg] >> 16) & 0xff) << 24)
			| (((State.regs[srcreg] >> 24) & 0xff) << 16));
}

// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
"swhw"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
			| ((State.regs[srcreg] >> 16) & 0xffff));
}

// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
"bsch"
*am33
*am33_2
{
  int temp, c, i;
  int srcreg, dstreg;
  int start;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  temp = State.regs[srcreg];
  start = (State.regs[dstreg] & 0x1f) - 1;
  if (start == -1)
    start = 31;
    
  c = 0;
  for (i = start; i >= 0; i--)
    {
      if (temp & (1 << i))
	{
	  c = 1;
	  State.regs[dstreg] = i;
	  break;
	}
    }

  if (i < 0)
    {
      c = 0;
      State.regs[dstreg] = 0;
    }
  PSW &= ~(PSW_C);
  PSW |= (c ? PSW_C : 0);
}


// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
"mov"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = EXTEND8 (IMM8);
}

// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
"movu"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = IMM8 & 0xff;
}

// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
"add"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);
  genericAdd (EXTEND8 (IMM8), dstreg);
}

// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
"addc"
*am33
*am33_2
{
  int dstreg, imm;
  int z, c, n, v;
  unsigned32 reg2, sum;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  imm = EXTEND8 (IMM8);
  reg2 = State.regs[dstreg];
  sum = imm + reg2 + ((PSW & PSW_C) != 0);
  State.regs[dstreg] = sum;

  z = ((PSW & PSW_Z) != 0) && (sum == 0);
  n = (sum & 0x80000000);
  c = (sum < imm) || (sum < reg2);
  v = ((reg2 & 0x80000000) == (imm & 0x80000000)
       && (reg2 & 0x80000000) != (sum & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
"sub"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  genericSub (EXTEND8 (IMM8), dstreg);
}

// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
"subc"
*am33
*am33_2
{
  int imm, dstreg;
  int z, c, n, v;
  unsigned32 reg2, difference;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  imm = EXTEND8 (IMM8);
  reg2 = State.regs[dstreg];
  difference = reg2 - imm - ((PSW & PSW_C) != 0);
  State.regs[dstreg] = difference;

  z = ((PSW & PSW_Z) != 0) && (difference == 0);
  n = (difference & 0x80000000);
  c = (imm > reg2);
  v = ((reg2 & 0x80000000) == (imm & 0x80000000)
       && (reg2 & 0x80000000) != (difference & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
"cmp"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RN0);
  genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
}

// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
"mov"
*am33
*am33_2
{
  int dstreg;