am33.igen

这个是LINUX下的GDB调度工具的源码

{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);
  genericAdd (1, dstreg);
}

// 1111 1001 1101 1000 Rn Rn; inc Rn
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
"inc4"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);
  genericAdd (4, dstreg);
}

// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
"cmp"
*am33
*am33_2
{
  int srcreg1, srcreg2;

  PC = cia;
  srcreg1 = translate_rreg (SD_, RN0);
  srcreg2 = translate_rreg (SD_, RM2);
  genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
}

// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
"mov"
*am33
*am33_2
{
  int dstreg, srcreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);
  srcreg = translate_xreg (SD_, XRM2);

  State.regs[dstreg] = State.regs[srcreg];
}

// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_xreg (SD_, XRN0);

  State.regs[dstreg] = State.regs[srcreg];
}

// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
"and"
*am33
*am33_2
{
  int srcreg, dstreg;
  int z, n;

  PC = cia;

  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] &= State.regs[srcreg];
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
"or"
*am33
*am33_2
{
  int srcreg, dstreg;
  int z, n;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] |= State.regs[srcreg];
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
"xor"
*am33
*am33_2
{
  int srcreg, dstreg;
  int z, n;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] ^= State.regs[srcreg];
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 0011 1001 Rn Rn; not Rn
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
"not"
*am33
*am33_2
{
  int dstreg;
  int z, n;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] = ~State.regs[dstreg];
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
"asr"
*am33
*am33_2
{
  int srcreg, dstreg;
  signed32 temp;
  int c, z, n;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  temp = State.regs[dstreg];
  c = temp & 1;
  temp >>= State.regs[srcreg];
  State.regs[dstreg] = temp;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
"lsr"
*am33
*am33_2
{
  int srcreg, dstreg;
  int z, n, c;

  PC = cia;

  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  c = State.regs[dstreg] & 1;
  State.regs[dstreg] >>= State.regs[srcreg];
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
"asl"
*am33
*am33_2
{
  int srcreg, dstreg;
  int z, n;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] <<= State.regs[srcreg];
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 0111 1001 Rn Rn; asl2 Rn
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
"asl2"
*am33
*am33_2
{
  int dstreg;
  int n, z;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  State.regs[dstreg] <<= 2;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 1000 1001 Rn Rn; ror Rn
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
"ror"
*am33
*am33_2
{
  int dstreg;
  int c, n, z;
  unsigned32 value;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  value = State.regs[dstreg];
  c = (value & 0x1);

  value >>= 1;
  value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
  State.regs[dstreg] = value;
  z = (value == 0);
  n = (value & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

// 1111 1001 1001 1001 Rn Rn; rol Rn
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
"rol"
*am33
*am33_2
{
  int dstreg;
  int c, n, z;
  unsigned32 value;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);

  value = State.regs[dstreg];
  c = (value & 0x80000000) ? 1 : 0;

  value <<= 1;
  value |= ((PSW & PSW_C) != 0);
  State.regs[dstreg] = value;
  z = (value == 0);
  n = (value & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
"mul"
*am33
*am33_2
{
  int srcreg, dstreg;
  unsigned64 temp;
  int n, z;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  temp = ((signed64)(signed32)State.regs[dstreg]
          *  (signed64)(signed32)State.regs[srcreg]);
  State.regs[dstreg] = temp & 0xffffffff;
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
"mulu"
*am33
*am33_2
{
  int srcreg, dstreg;
  unsigned64 temp;
  int n, z;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  temp = ((unsigned64)State.regs[dstreg]
          * (unsigned64)State.regs[srcreg]);
  State.regs[dstreg] = temp & 0xffffffff;
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
"div"
*am33
*am33_2
{
  int srcreg, dstreg;
  signed64 temp;
  int n, z;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  temp = State.regs[REG_MDR];
  temp <<= 32;
  temp |= State.regs[dstreg];
  State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
  temp /= (signed32)State.regs[srcreg];
  State.regs[dstreg] = temp & 0xffffffff;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
"divu"
*am33
*am33_2
{
  int srcreg, dstreg;
  unsigned64 temp;
  int n, z;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  temp = State.regs[REG_MDR];
  temp <<= 32;
  temp |= State.regs[dstreg];
  State.regs[REG_MDR] = temp % State.regs[srcreg];
  temp /= State.regs[srcreg];
  State.regs[dstreg] = temp & 0xffffffff;
  z = (State.regs[dstreg] == 0);
  n = (State.regs[dstreg] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}


// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_word (State.regs[srcreg]);
}

// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_word (State.regs[dstreg], State.regs[srcreg]);
}

// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_byte (State.regs[srcreg]);
}

// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_byte (State.regs[dstreg], State.regs[srcreg]);
}

// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_half (State.regs[srcreg]);
}

// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_half (State.regs[dstreg], State.regs[srcreg]);
}

// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_word (State.regs[srcreg]);
  State.regs[srcreg] += 4;
}

// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_word (State.regs[dstreg], State.regs[srcreg]);
  State.regs[dstreg] += 4;
}

// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
"mov"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_word (State.regs[REG_SP]);
}

// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
"mov"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_word (State.regs[REG_SP], State.regs[srcreg]);
}

// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
"movbu"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_byte (State.regs[REG_SP]);
}

// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
"movbu"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_byte (State.regs[REG_SP], State.regs[srcreg]);
}

// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
"movhu"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_half (State.regs[REG_SP]);
}

// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  store_half (State.regs[REG_SP], State.regs[srcreg]);
}

// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM0);
  dstreg = translate_rreg (SD_, RN2);
  State.regs[dstreg] = load_half (State.regs[srcreg]);
  State.regs[srcreg] += 2;
}

// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
"movhu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  store_half (State.regs[dstreg], State.regs[srcreg]);
  State.regs[dstreg] += 2;
}


// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac