am33.igen

这个是LINUX下的GDB调度工具的源码

// Helper:            
//
// Given an extended register number, translate it into an index into the
// register array.  This is necessary as the upper 8 extended registers are
// actually synonyms for the d0-d3/a0-a3 registers.
//
//

:function:::int:translate_rreg:int rreg
{
  
  /* The higher register numbers actually correspond to the
     basic machine's address and data registers.  */
  if (rreg > 7 && rreg < 12)
    return REG_A0 + rreg - 8;
  else if (rreg > 11 && rreg < 16)
    return REG_D0 + rreg - 12;
  else
    return REG_E0 + rreg;
}

:function:::int:translate_xreg:int xreg
{
  switch (xreg)
    {
    case 0:
      return REG_SP;
    case 1:
      return REG_MDRQ;
    case 2:
      return REG_MCRH;
    case 3:
      return REG_MCRL;
    case 4:
      return REG_MCVF;
    default:
      sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__);
    }
}

// 1111 0000 0010 00An; mov USP,An
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  State.regs[REG_A0 + AN0] = State.regs[REG_USP];
}


// 1111 0000 0010 01An; mov SSP,An
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
}


// 1111 0000 0010 10An; mov MSP,An
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
}


// 1111 0000 0010 11An; mov PC,An
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  State.regs[REG_A0 + AN0] = PC;
}


// 1111 0000 0011 Am00; mov Am,USP
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  State.regs[REG_USP] = State.regs[REG_A0 + AM1];
}

// 1111 0000 0011 Am01; mov Am,SSP
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
}

// 1111 0000 0011 Am10; mov Am,MSP
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
}


// 1111 0000 1110 imm4; syscall
8.0xf0+4.0xe,IMM4:D0t:::syscall
"syscall"
*am33
*am33_2
{
  unsigned32 sp, next_pc;

  PC = cia;
  sp = State.regs[REG_SP];
  next_pc = State.regs[REG_PC] + 2;
  store_word (sp - 4, next_pc);
  store_word (sp - 8, PSW);
  State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
  nia = PC;
}


// 1111 0010 1110 11Dn; mov EPSW,Dn
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  State.regs[REG_D0 + DN0] = PSW;
}


// 1111 0010 1111 Dm01; mov Dm,EPSW
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
"mov"
*am33
*am33_2
{
  PC = cia;
  PSW = State.regs[REG_D0 + DM1];
}

// 1111 0101 00Am Rn; mov Am,Rn
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
"mov"
*am33
*am33_2
{
  int destreg = translate_rreg (SD_, RN0);

  PC = cia;
  State.regs[destreg] = State.regs[REG_A0 + AM1];
}

// 1111 0101 01Dm Rn; mov Dm,Rn
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
"mov"
*am33
*am33_2
{
  int destreg = translate_rreg (SD_, RN0);

  PC = cia;
  State.regs[destreg] = State.regs[REG_D0 + DM1];
}

// 1111 0101 10Rm An; mov Rm,An
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
"mov"
*am33
*am33_2
{
  int destreg = translate_rreg (SD_, RM1);

  PC = cia;
  State.regs[REG_A0 + AN0] = State.regs[destreg];
}

// 1111 0101 11Rm Dn; mov Rm,Dn
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
"mov"
*am33
*am33_2
{
  int destreg = translate_rreg (SD_, RM1);

  PC = cia;
  State.regs[REG_D0 + DN0] = State.regs[destreg];
}


// 1111 1000 1100 1110 regs....; movm (USP),regs
8.0xf8+8.0xce+8.REGS:D1a:::movm
"movm"
*am33
*am33_2
{
  unsigned32 usp = State.regs[REG_USP];
  unsigned32 mask;

  PC = cia;
  mask = REGS;

  if (mask & 0x8)
    {
      usp += 4;
      State.regs[REG_LAR] = load_word (usp);
      usp += 4;
      State.regs[REG_LIR] = load_word (usp);
      usp += 4;
      State.regs[REG_MDR] = load_word (usp);
      usp += 4;
      State.regs[REG_A0 + 1] = load_word (usp);
      usp += 4;
      State.regs[REG_A0] = load_word (usp);
      usp += 4;
      State.regs[REG_D0 + 1] = load_word (usp);
      usp += 4;
      State.regs[REG_D0] = load_word (usp);
      usp += 4;
    }

  if (mask & 0x10)
    {
      State.regs[REG_A0 + 3] = load_word (usp);
      usp += 4;
    }

  if (mask & 0x20)
    {
      State.regs[REG_A0 + 2] = load_word (usp);
      usp += 4;
    }

  if (mask & 0x40)
    {
      State.regs[REG_D0 + 3] = load_word (usp);
      usp += 4;
    }

  if (mask & 0x80)
    {
      State.regs[REG_D0 + 2] = load_word (usp);
      usp += 4;
    }

  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
      )
    {
      if (mask & 0x1)
	{
	  /* Need to restore MDQR, MCRH, MCRL, and MCVF */
	  usp += 16;
	  State.regs[REG_E0 + 1] = load_word (usp);
	  usp += 4;
	  State.regs[REG_E0 + 0] = load_word (usp);
	  usp += 4;
	}

      if (mask & 0x2)
        {
	  State.regs[REG_E0 + 7] = load_word (usp);
	  usp += 4;
	  State.regs[REG_E0 + 6] = load_word (usp);
	  usp += 4;
	  State.regs[REG_E0 + 5] = load_word (usp);
	  usp += 4;
	  State.regs[REG_E0 + 4] = load_word (usp);
	  usp += 4;
	}

      if (mask & 0x4)
	{
	  State.regs[REG_E0 + 3] = load_word (usp);
	  usp += 4;
	  State.regs[REG_E0 + 2] = load_word (usp);
	  usp += 4;
	}
    }

  /* And make sure to update the stack pointer.  */
  State.regs[REG_USP] = usp;
}

// 1111 1000 1100 1111 regs....; movm (USP),regs
8.0xf8+8.0xcf+8.REGS:D1b:::movm
"movm"
*am33
*am33_2
{
  unsigned32 usp = State.regs[REG_USP];
  unsigned32 mask;

  PC = cia;
  mask = REGS;

  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
      )
    {
      if (mask & 0x4)
	{
	  usp -= 4;
	  store_word (usp, State.regs[REG_E0 + 2]);
	  usp -= 4;
	  store_word (usp, State.regs[REG_E0 + 3]);
	}

      if (mask & 0x2)
        {
	  usp -= 4;
	  store_word (usp, State.regs[REG_E0 + 4]);
	  usp -= 4;
	  store_word (usp, State.regs[REG_E0 + 5]);
	  usp -= 4;
	  store_word (usp, State.regs[REG_E0 + 6]);
	  usp -= 4;
	  store_word (usp, State.regs[REG_E0 + 7]);
	}

      if (mask & 0x1)
	{
	  usp -= 4;
	  store_word (usp, State.regs[REG_E0 + 0]);
	  usp -= 4;
	  store_word (usp, State.regs[REG_E0 + 1]);
	  usp -= 16;
	  /* Need to save MDQR, MCRH, MCRL, and MCVF */
	}
    }

  if (mask & 0x80)
    {
      usp -= 4;
      store_word (usp, State.regs[REG_D0 + 2]);
    }

  if (mask & 0x40)
    {
      usp -= 4;
      store_word (usp, State.regs[REG_D0 + 3]);
    }

  if (mask & 0x20)
    {
      usp -= 4;
      store_word (usp, State.regs[REG_A0 + 2]);
    }

  if (mask & 0x10)
    {
      usp -= 4;
      store_word (usp, State.regs[REG_A0 + 3]);
    }

  if (mask & 0x8)
    {
      usp -= 4;
      store_word (usp, State.regs[REG_D0]);
      usp -= 4;
      store_word (usp, State.regs[REG_D0 + 1]);
      usp -= 4;
      store_word (usp, State.regs[REG_A0]);
      usp -= 4;
      store_word (usp, State.regs[REG_A0 + 1]);
      usp -= 4;
      store_word (usp, State.regs[REG_MDR]);
      usp -= 4;
      store_word (usp, State.regs[REG_LIR]);
      usp -= 4;
      store_word (usp, State.regs[REG_LAR]);
      usp -= 4;
    }

  /* And make sure to update the stack pointer.  */
  State.regs[REG_USP] = usp;
}

// 1111 1100 1111 1100 imm32...; and imm32,EPSW 
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
"and"
*am33
*am33_2
{
  PC = cia;
  PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
}

// 1111 1100 1111 1101 imm32...; or imm32,EPSW 
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
"or"
*am33
*am33_2
{
  PC = cia;
  PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
}

// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
"mov"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;

  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = State.regs[srcreg];
}

// 1111 1001 0001 1000 Rn Rn; ext Rn
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
"mov"
*am33
*am33_2
{
  int srcreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RN0);
  if (State.regs[srcreg] & 0x80000000)
    State.regs[REG_MDR] = -1;
  else
    State.regs[REG_MDR] = 0;
}

// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
"extb"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
}

// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
"extbu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = State.regs[srcreg] & 0xff;
}

// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
"exth"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
}

// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
"exthu"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = State.regs[srcreg] & 0xffff;
}

// 1111 1001 0110 1000 Rn Rn; clr Rn
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
"clr"
*am33
*am33_2
{
  int dstreg;

  PC = cia;
  dstreg = translate_rreg (SD_, RN0);
  State.regs[dstreg] = 0;
  PSW |= PSW_Z;
  PSW &= ~(PSW_V | PSW_C | PSW_N);
}

// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
"add"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  genericAdd (State.regs[srcreg], dstreg);
}

// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
"addc"
*am33
*am33_2
{
  int srcreg, dstreg;
  int z, c, n, v;
  unsigned32 reg1, reg2, sum;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  reg1 = State.regs[srcreg];
  reg2 = State.regs[dstreg];
  sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
  State.regs[dstreg] = sum;

  z = ((PSW & PSW_Z) != 0) && (sum == 0);
  n = (sum & 0x80000000);
  c = (sum < reg1) || (sum < reg2);
  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
       && (reg2 & 0x80000000) != (sum & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
"sub"
*am33
*am33_2
{
  int srcreg, dstreg;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);
  genericSub (State.regs[srcreg], dstreg);
}

// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
"subc"
*am33
*am33_2
{
  int srcreg, dstreg;
  int z, c, n, v;
  unsigned32 reg1, reg2, difference;

  PC = cia;
  srcreg = translate_rreg (SD_, RM2);
  dstreg = translate_rreg (SD_, RN0);

  reg1 = State.regs[srcreg];
  reg2 = State.regs[dstreg];
  difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
  State.regs[dstreg] = difference;

  z = ((PSW & PSW_Z) != 0) && (difference == 0);
  n = (difference & 0x80000000);
  c = (reg1 > reg2);
  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
       && (reg2 & 0x80000000) != (difference & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

// 1111 1001 1011 1000 Rn Rn; inc Rn
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
"inc"
*am33
*am33_2