mips.igen

这个是LINUX下的GDB调度工具的源码

  if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
    {
      DELAY_SLOT (NIA + offset);
    }
  else
    NULLIFY_NEXT_INSTRUCTION ();
}



000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if ((signed_word) GPR[RS] >= 0)
    {
      DELAY_SLOT (NIA + offset);
    }
}



000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if (RS == 31)
    Unpredictable ();
  RA = (CIA + 8);
  if ((signed_word) GPR[RS] >= 0)
    {
      DELAY_SLOT (NIA + offset);
    }
}



000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
"bgezall r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if (RS == 31)
    Unpredictable ();
  RA = (CIA + 8);
  /* NOTE: The branch occurs AFTER the next instruction has been
     executed */
  if ((signed_word) GPR[RS] >= 0)
    {
      DELAY_SLOT (NIA + offset);
    }
  else
    NULLIFY_NEXT_INSTRUCTION ();
}



000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if ((signed_word) GPR[RS] >= 0)
    {
      DELAY_SLOT (NIA + offset);
    }
  else
    NULLIFY_NEXT_INSTRUCTION ();
}



000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if ((signed_word) GPR[RS] > 0)
    {
      DELAY_SLOT (NIA + offset);
    }
}



010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
"bgtzl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  /* NOTE: The branch occurs AFTER the next instruction has been
     executed */
  if ((signed_word) GPR[RS] > 0)
    {
      DELAY_SLOT (NIA + offset);
    }
  else
    NULLIFY_NEXT_INSTRUCTION ();
}



000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  /* NOTE: The branch occurs AFTER the next instruction has been
     executed */
  if ((signed_word) GPR[RS] <= 0)
    {
      DELAY_SLOT (NIA + offset);
    }
}



010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if ((signed_word) GPR[RS] <= 0)
    {
      DELAY_SLOT (NIA + offset);
    }
  else
    NULLIFY_NEXT_INSTRUCTION ();
}



000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if ((signed_word) GPR[RS] < 0)
    {
      DELAY_SLOT (NIA + offset);
    }
}



000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if (RS == 31)
    Unpredictable ();
  RA = (CIA + 8);
  /* NOTE: The branch occurs AFTER the next instruction has been
     executed */
  if ((signed_word) GPR[RS] < 0)
    {
      DELAY_SLOT (NIA + offset);
    }
}



000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
"bltzall r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if (RS == 31)
    Unpredictable ();
  RA = (CIA + 8);
  if ((signed_word) GPR[RS] < 0)
    {
      DELAY_SLOT (NIA + offset);
    }
  else
    NULLIFY_NEXT_INSTRUCTION ();
}



000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
"bltzl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  /* NOTE: The branch occurs AFTER the next instruction has been
     executed */
  if ((signed_word) GPR[RS] < 0)
    {
      DELAY_SLOT (NIA + offset);
    }
  else
    NULLIFY_NEXT_INSTRUCTION ();
}



000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
    {
      DELAY_SLOT (NIA + offset);
    }
}



010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
"bnel r<RS>, r<RT>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  address_word offset = EXTEND16 (OFFSET) << 2;
  if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
    {
      DELAY_SLOT (NIA + offset);
    }
  else
    NULLIFY_NEXT_INSTRUCTION ();
}



000000,20.CODE,001101:SPECIAL:32::BREAK
"break %#lx<CODE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
*r3900:
{
  /* Check for some break instruction which are reserved for use by the simulator.  */
  unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
  if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
      break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
    {
      sim_engine_halt (SD, CPU, NULL, cia,
                       sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
    }
  else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
           break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
    {
      if (STATE & simDELAYSLOT)
        PC = cia - 4; /* reference the branch instruction */
      else
        PC = cia;
      SignalException (BreakPoint, instruction_0);
    }

  else
    {
      /* If we get this far, we're not an instruction reserved by the sim.  Raise
	 the exception. */
      SignalException (BreakPoint, instruction_0);
    }
}



011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
"clo r<RD>, r<RS>"
*mips32:
*mips64:
*vr5500:
{
  unsigned32 temp = GPR[RS];
  unsigned32 i, mask;
  if (RT != RD)
    Unpredictable ();
  if (NotWordValue (GPR[RS]))
    Unpredictable ();
  TRACE_ALU_INPUT1 (GPR[RS]);
  for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
    {
      if ((temp & mask) == 0)
	break;
      mask >>= 1;
    }
  GPR[RD] = EXTEND32 (i);
  TRACE_ALU_RESULT (GPR[RD]);
}



011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
"clz r<RD>, r<RS>"
*mips32:
*mips64:
*vr5500:
{
  unsigned32 temp = GPR[RS];
  unsigned32 i, mask;
  if (RT != RD)
    Unpredictable ();
  if (NotWordValue (GPR[RS]))
    Unpredictable ();
  TRACE_ALU_INPUT1 (GPR[RS]);
  for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
    {
      if ((temp & mask) != 0)
	break;
      mask >>= 1;
    }
  GPR[RD] = EXTEND32 (i);
  TRACE_ALU_RESULT (GPR[RD]);
}



000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
"dadd r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*vr4100:
*vr5000:
{
  check_u64 (SD_, instruction_0);
  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
  {
    ALU64_BEGIN (GPR[RS]);
    ALU64_ADD (GPR[RT]);
    ALU64_END (GPR[RD]);   /* This checks for overflow.  */
  }
  TRACE_ALU_RESULT (GPR[RD]);
}



011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
"daddi r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*vr4100:
*vr5000:
{
  check_u64 (SD_, instruction_0);
  TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
  {
    ALU64_BEGIN (GPR[RS]);
    ALU64_ADD (EXTEND16 (IMMEDIATE));
    ALU64_END (GPR[RT]);   /* This checks for overflow.  */
  }
  TRACE_ALU_RESULT (GPR[RT]);
}



:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
{
  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
  GPR[rt] = GPR[rs] + EXTEND16 (immediate);
  TRACE_ALU_RESULT (GPR[rt]);
}

011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
"daddiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*vr4100:
*vr5000:
{
  check_u64 (SD_, instruction_0);
  do_daddiu (SD_, RS, RT, IMMEDIATE);
}



:function:::void:do_daddu:int rs, int rt, int rd
{
  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
  GPR[rd] = GPR[rs] + GPR[rt];
  TRACE_ALU_RESULT (GPR[rd]);
}

000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
"daddu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*vr4100:
*vr5000:
{
  check_u64 (SD_, instruction_0);
  do_daddu (SD_, RS, RT, RD);
}



011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
*vr5500:
{
  unsigned64 temp = GPR[RS];
  unsigned32 i;
  unsigned64 mask;
  check_u64 (SD_, instruction_0);
  if (RT != RD)
    Unpredictable ();
  TRACE_ALU_INPUT1 (GPR[RS]);
  for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
    {
      if ((temp & mask) == 0)
	break;
      mask >>= 1;
    }
  GPR[RD] = EXTEND32 (i);
  TRACE_ALU_RESULT (GPR[RD]);
}



011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
*vr5500:
{
  unsigned64 temp = GPR[RS];
  unsigned32 i;
  unsigned64 mask;
  check_u64 (SD_, instruction_0);
  if (RT != RD)
    Unpredictable ();
  TRACE_ALU_INPUT1 (GPR[RS]);
  for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
    {
      if ((temp & mask) != 0)
	break;
      mask >>= 1;
    }
  GPR[RD] = EXTEND32 (i);
  TRACE_ALU_RESULT (GPR[RD]);
}



:function:::void:do_ddiv:int rs, int rt
{
  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
  {
    signed64 n = GPR[rs];
    signed64 d = GPR[rt];
    signed64 hi;
    signed64 lo;
    if (d == 0)
      {
	lo = SIGNED64 (0x8000000000000000);
	hi = 0;
      }
    else if (d == -1 && n == SIGNED64 (0x8000000000000000))
      {
	lo = SIGNED64 (0x8000000000000000);
	hi = 0;
      }
    else
      {
	lo = (n / d);
	hi = (n % d);
      }
    HI = hi;
    LO = lo;
  }
  TRACE_ALU_RESULT2 (HI, LO);
}

000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*vr4100:
*vr5000:
{
  check_u64 (SD_, instruction_0);
  do_ddiv (SD_, RS, RT);
}



:function:::void:do_ddivu:int rs, int rt
{
  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
  {
    unsigned64 n = GPR[rs];
    unsigned64 d = GPR[rt];
    unsigned64 hi;
    unsigned64 lo;
    if (d == 0)
      {
	lo = SIGNED64 (0x8000000000000000);
	hi = 0;
      }
    else
      {
	lo = (n / d);
	hi = (n % d);
      }
    HI = hi;
    LO = lo;
  }
  TRACE_ALU_RESULT2 (HI, LO);
}

000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
"ddivu r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
*vr4100:
*vr5000:
{
  check_u64 (SD_, instruction_0);
  do_ddivu (SD_, RS, RT);
}



:function:::void:do_div:int rs, int rt
{
  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
  {
    signed32 n = GPR[rs];
    signed32 d = GPR[rt];
    if (d == 0)
      {
	LO = EXTEND32 (0x80000000);
	HI = EXTEND32 (0);
      }
    else if (n == SIGNED32 (0x80000000) && d == -1)
      {
	LO = EXTEND32 (0x80000000);
	HI = EXTEND32 (0);
      }
    else
      {
	LO = EXTEND32 (n / d);
	HI = EXTEND32 (n % d);
      }