dv-tx3904sio.c

这个是LINUX下的GDB调度工具的源码

/*  This file is part of the program GDB, the GNU debugger.
    
    Copyright (C) 1998, 1999 Free Software Foundation, Inc.
    Contributed by Cygnus Solutions.
    
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
    
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
    
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
    
    */


#include "sim-main.h"
#include "hw-main.h"
#include "dv-sockser.h"
#include "sim-assert.h"


/* DEVICE

   
   tx3904sio - tx3904 serial I/O

   
   DESCRIPTION

   
   Implements one tx3904 serial I/O controller described in the tx3904
   user guide.  Three instances are required for SIO0 and SIO1 within
   the tx3904, at different base addresses.

   Both internal and system clocks are synthesized as divided versions
   of the simulator clock.
   
   There is no support for:
    - CTS/RTS flow control
    - baud rate emulation - use infinite speed instead
    - general frame format - use 8N1
    - multi-controller system
    - DMA - use interrupt-driven or polled-I/O instead


   PROPERTIES


   reg <base> <length>

   Base of SIO control register bank.  <length> must equal 0x100.
   Register offsets:       0: SLCR: line control register
                           4: SLSR: line status register
                           8: SDICR: DMA/interrupt control register
                          12: SDISR: DMA/interrupt status register
                          16: SFCR: FIFO control register
			  20: SBGR: baud rate control register
			  32: transfer FIFO buffer
			  48: transfer FIFO buffer

   backend {tcp | stdio}

   Use dv-sockser TCP-port backend or stdio for backend.  Default: stdio.



   PORTS


   int (output)

   Interrupt port.  An event is generated when a timer interrupt
   occurs.


   reset (input)

   Reset port.

   */



/* static functions */

struct tx3904sio_fifo;

static void tx3904sio_tickle(struct hw*);
static int tx3904sio_fifo_nonempty(struct hw*, struct tx3904sio_fifo*);
static char tx3904sio_fifo_pop(struct hw*, struct tx3904sio_fifo*);
static void tx3904sio_fifo_push(struct hw*, struct tx3904sio_fifo*, char);
static void tx3904sio_fifo_reset(struct hw*, struct tx3904sio_fifo*);
static void tx3904sio_poll(struct hw*, void* data);


/* register numbers; each is one word long */
enum 
{
  SLCR_REG = 0,
  SLSR_REG = 1,
  SDICR_REG = 2,
  SDISR_REG = 3,
  SFCR_REG = 4,
  SBGR_REG = 5,
  TFIFO_REG = 8,
  SFIFO_REG = 12,
};



/* port ID's */

enum
 {
  RESET_PORT,
  INT_PORT,
};


static const struct hw_port_descriptor tx3904sio_ports[] = 
{
  { "int", INT_PORT, 0, output_port, },
  { "reset", RESET_PORT, 0, input_port, },
  { NULL, },
};



/* Generic FIFO */
struct tx3904sio_fifo 
{
  int size, used;
  unsigned_1 *buffer;
};



/* The timer/counter register internal state.  Note that we store
   state using the control register images, in host endian order. */

struct tx3904sio 
{
  address_word base_address; /* control register base */
  enum {sio_tcp, sio_stdio} backend; /* backend */

  struct tx3904sio_fifo rx_fifo, tx_fifo; /* FIFOs */

  unsigned_4 slcr;
#define SLCR_WR_MASK        0xe17f0000U
#define SLCR_SET_BYTE(c,o,b) ((c)->slcr = SLCR_WR_MASK & (((c)->slcr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
  unsigned_4 slsr;
#define SLSR_WR_MASK        0x00000000 /* UFER/UPER/UOER unimplemented */
  unsigned_4 sdicr;
#define SDICR_WR_MASK       0x000f0000U
#define SDICR_SET_BYTE(c,o,b) ((c)->sdicr = SDICR_WR_MASK & (((c)->sdicr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
#define SDICR_GET_SDMAE(c)  ((c)->sdicr & 0x00080000)
#define SDICR_GET_ERIE(c)   ((c)->sdicr & 0x00040000)
#define SDICR_GET_TDIE(c)   ((c)->sdicr & 0x00020000)
#define SDICR_GET_RDIE(c)   ((c)->sdicr & 0x00010000)
  unsigned_4 sdisr;
#define SDISR_WR_MASK       0x00070000U
#define SDISR_SET_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
#define SDISR_CLEAR_FLAG_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) & ((b)<< (o)*8)))
#define SDISR_GET_TDIS(c)   ((c)->sdisr & 0x00020000)
#define SDISR_SET_TDIS(c)   ((c)->sdisr |= 0x00020000)
#define SDISR_GET_RDIS(c)   ((c)->sdisr & 0x00010000)
#define SDISR_SET_RDIS(c)   ((c)->sdisr |= 0x00010000)
  unsigned_4 sfcr;
#define SFCR_WR_MASK       0x001f0000U
#define SFCR_SET_BYTE(c,o,b) ((c)->sfcr = SFCR_WR_MASK & (((c)->sfcr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
#define SFCR_GET_TFRST(c)   ((c)->sfcr & 0x00040000)
#define SFCR_GET_RFRST(c)   ((c)->sfcr & 0x00020000)
#define SFCR_GET_FRSTE(c)   ((c)->sfcr & 0x00010000)
  unsigned_4 sbgr;
#define SBGR_WR_MASK       0x03ff0000U
#define SBGR_SET_BYTE(c,o,b) ((c)->sbgr = SBGR_WR_MASK & (((c)->sbgr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))

  /* Periodic I/O polling */
  struct hw_event* poll_event;
};



/* Finish off the partially created hw device.  Attach our local
   callbacks.  Wire up our port names etc */

static hw_io_read_buffer_method tx3904sio_io_read_buffer;
static hw_io_write_buffer_method tx3904sio_io_write_buffer;
static hw_port_event_method tx3904sio_port_event;


static void
attach_tx3904sio_regs (struct hw *me,
		      struct tx3904sio *controller)
{
  unsigned_word attach_address;
  int attach_space;
  unsigned attach_size;
  reg_property_spec reg;

  if (hw_find_property (me, "reg") == NULL)
    hw_abort (me, "Missing \"reg\" property");

  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
    hw_abort (me, "\"reg\" property must contain one addr/size entry");

  hw_unit_address_to_attach_address (hw_parent (me),
				     &reg.address,
				     &attach_space,
				     &attach_address,
				     me);
  hw_unit_size_to_attach_size (hw_parent (me),
			       &reg.size,
			       &attach_size, me);

  hw_attach_address (hw_parent (me), 0,
		     attach_space, attach_address, attach_size,
		     me);

  if(hw_find_property(me, "backend") != NULL)
    {
      const char* value = hw_find_string_property(me, "backend");
      if(! strcmp(value, "tcp"))
	controller->backend = sio_tcp;
      else if(! strcmp(value, "stdio"))
	controller->backend = sio_stdio;
      else
	hw_abort(me, "illegal value for backend parameter `%s': use tcp or stdio", value);
    }

  controller->base_address = attach_address;
}


static void
tx3904sio_finish (struct hw *me)
{
  struct tx3904sio *controller;

  controller = HW_ZALLOC (me, struct tx3904sio);
  set_hw_data (me, controller);
  set_hw_io_read_buffer (me, tx3904sio_io_read_buffer);
  set_hw_io_write_buffer (me, tx3904sio_io_write_buffer);
  set_hw_ports (me, tx3904sio_ports);
  set_hw_port_event (me, tx3904sio_port_event);

  /* Preset defaults */
  controller->backend = sio_stdio;

  /* Attach ourself to our parent bus */
  attach_tx3904sio_regs (me, controller);

  /* Initialize to reset state */
  tx3904sio_fifo_reset(me, & controller->rx_fifo);
  tx3904sio_fifo_reset(me, & controller->tx_fifo);
  controller->slsr = controller->sdicr
    = controller->sdisr = controller->sfcr
    = controller->sbgr = 0;
  controller->slcr = 0x40000000; /* set TWUB */
  controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */
  controller->poll_event = NULL;
}



/* An event arrives on an interrupt port */

static void
tx3904sio_port_event (struct hw *me,
		     int my_port,
		     struct hw *source,
		     int source_port,
		     int level)
{
  struct tx3904sio *controller = hw_data (me);

  switch (my_port)
    {
    case RESET_PORT:
      {
	HW_TRACE ((me, "reset"));

	tx3904sio_fifo_reset(me, & controller->rx_fifo);
	tx3904sio_fifo_reset(me, & controller->tx_fifo);
	controller->slsr = controller->sdicr
	  = controller->sdisr = controller->sfcr
	  = controller->sbgr = 0;
	controller->slcr = 0x40000000; /* set TWUB */
	controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */
	/* Don't interfere with I/O poller. */
	break;
      }

    default:
      hw_abort (me, "Event on unknown port %d", my_port);
      break;
    }
}


/* generic read/write */

static unsigned
tx3904sio_io_read_buffer (struct hw *me,
			 void *dest,