m16.igen

这个是LINUX下的GDB调度工具的源码

// -*- C -*-
//
//
// MIPS Architecture:
//
//        CPU Instruction Set (mips16)
//

// The instructions in this section are ordered according
// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.


// The MIPS16 codes registers in a special way, map from one to the other.
// :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)

:compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0)

:compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0))
:compute:::int:R32:R32L,R32H:((R32H << 3) | R32L)

:compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0))

:compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0))


// Load and Store Instructions


10000,3.RX,3.RY,5.IMMED:RRI:16::LB
"lb r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
}

11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB
"lb r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
}



10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
"lbu r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
}

11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU
"lbu r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
}



10001,3.RX,3.RY,5.IMMED:RRI:16::LH
"lh r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
}

11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH
"lh r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
}



10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
"lhu r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
}

11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU
"lhu r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
}



10011,3.RX,3.RY,5.IMMED:RRI:16::LW
"lw r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
}

11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW
"lw r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
}



10110,3.RX,8.IMMED:RI:16::LWPC
"lw r<TRX>, <IMMED> (PC)"
*mips16:
*vr4100:
{
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
				basepc (SD_) & ~3, IMMED << 2));
}

11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC
"lw r<TRX>, <IMMEDIATE> (PC)"
*mips16:
*vr4100:
{
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE)));
}



10010,3.RX,8.IMMED:RI:16::LWSP
"lw r<TRX>, <IMMED> (SP)"
*mips16:
*vr4100:
{
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
}

11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP
"lw r<TRX>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE)));
}



10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
"lwu r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
}

11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU
"lwu r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE));
}



00111,3.RX,3.RY,5.IMMED:RRI:16::LD
"ld r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
}

11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LD
"ld r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
}



11111,100,3.RY,5.IMMED:RI64:16::LDPC
"ld r<TRY>, <IMMED> (PC)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
		      basepc (SD_) & ~7, IMMED << 3);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC
"ld r<TRY>, <IMMEDIATE> (PC)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE));
}



11111,000,3.RY,5.IMMED:RI64:16::LDSP
"ld r<TRY>, <IMMED> (SP)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP
"ld r<TRY>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE));
}



11000,3.RX,3.RY,5.IMMED:RRI:16::SB
"sb r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB
"sb r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
}



11001,3.RX,3.RY,5.IMMED:RRI:16::SH
"sh r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH
"sh r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
}



11011,3.RX,3.RY,5.IMMED:RRI:16::SW
"sw r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW
"sw r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
}



11010,3.RX,8.IMMED:RI:16::SWSP
"sw r<TRX>, <IMMED> (SP)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP
"sw r<TRX>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]);
}



01100,010,8.IMMED:I8:16::SWRASP
"sw r<RAIDX>, <IMMED> (SP)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
}

11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP
"sw r<RAIDX>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA);
}



01111,3.RX,3.RY,5.IMMED:RRI:16::SD
"sd r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
}

11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD
"sd r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
}



11111,001,3.RY,5.IMMED:RI64:16::SDSP
"sd r<TRY>, <IMMED> (SP)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP
"sd r<TRY>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]);
}



11111,010,8.IMMED:I64:16::SDRASP
"sd r<RAIDX>, <IMMED> (SP)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP
"sd r<RAIDX>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
  do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA);
}



// ALU Immediate Instructions


01101,3.RX,8.IMMED:RI:16::LI
"li r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
  do_ori (SD_, 0, TRX, IMMED);
}

11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI
"li r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_ori (SD_, 0, TRX, IMMEDIATE);
}



01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU
"addiu r<TRY>, r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
  do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}

11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU
"addiu r<TRY>, r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
}



01001,3.RX,8.IMMED:RI:16::ADDIU8
"addiu r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
  do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
}

11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8
"addiu r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE));
}



01100,011,8.IMMED:I8:16::ADJSP
"addiu SP, <IMMED>"
*mips16:
*vr4100:
{
  do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}

11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP
"addiu SP, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
}



00001,3.RX,8.IMMED:RI:16::ADDIUPC
"addiu r<TRX>, PC, <IMMED>"
*mips16:
*vr4100:
{
  unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2);
  GPR[TRX] = EXTEND32 (temp);
}

11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC
"addiu r<TRX>, PC, <IMMEDIATE>"
*mips16:
*vr4100:
{
  unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
  GPR[TRX] = EXTEND32 (temp);
}



00000,3.RX,8.IMMED:RI:16::ADDIUSP
"addiu r<TRX>, SP, <IMMED>"
*mips16:
*vr4100:
{
  do_addiu (SD_, SPIDX, TRX, IMMED << 2);
}

11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP
"addiu r<TRX>, SP, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE));
}



01000,3.RX,3.RY,1,4.IMMED:RRI-A:16::DADDIU
"daddiu r<TRY>, r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
  do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}

11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16::DADDIU
"daddiu r<TRY>, r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
}



11111,101,3.RY,5.IMMED:RI64:16::DADDIU5
"daddiu r<TRY>, <IMMED>"
*mips16:
*vr4100:
{
  do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
}

11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIU5
"daddiu r<TRY>, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_daddiu (SD_, TRY, TRY, EXTEND16 (IMMEDIATE));
}



11111,011,8.IMMED:I64:16::DADJSP
"daddiu SP, <IMMED>"
*mips16:
*vr4100:
{
  do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16::DADJSP
"daddiu SP, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
}



11111,110,3.RY,5.IMMED:RI64:16::DADDIUPC
"daddiu r<TRY>, PC, <IMMED>"
*mips16:
*vr4100:
{
  GPR[TRY] = (basepc (SD_) & ~3) + (IMMED << 2);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUPC
"daddiu r<TRY>, PC, <IMMEDIATE>"
*mips16:
*vr4100:
{
  GPR[TRY] = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
}



11111,111,3.RY,5.IMMED:RI64:16::DADDIUSP
"daddiu r<TRY>, SP, <IMMED>"
*mips16:
*vr4100:
{
  do_daddiu (SD_, SPIDX, TRY, IMMED << 2);
}

11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUSP
"daddiu r<TRY>, SP, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_daddiu (SD_, SPIDX, TRY, EXTEND16 (IMMEDIATE));
}



01010,3.RX,8.IMMED:RI:16::SLTI
"slti r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
  do_slti (SD_, TRX, T8IDX, IMMED);
}

11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI
"slti r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_slti (SD_, TRX, T8IDX, IMMEDIATE);
}



01011,3.RX,8.IMMED:RI:16::SLTIU
"sltiu r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
  do_sltiu (SD_, TRX, T8IDX, IMMED);
}

11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU
"sltiu r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
  do_sltiu (SD_, TRX, T8IDX, IMMEDIATE);
}



11101,3.RX,3.RY,01010:RR:16::CMP
"cmp r<TRX>, r<TRY>"
*mips16:
*vr4100: