changelog

这个是LINUX下的GDB调度工具的源码

	* sim-main.h (GETFCC): Return an unsigned value.

Tue Mar  3 13:21:37 1998  Andrew Cagney  <[e-mail]>

	* mips.igen (DIV): Fix check for -1 / MIN_INT.
	(DADD): Result destination is RD not RT.

Fri Feb 27 13:49:49 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h (HIACCESS, LOACCESS): Always define.

	* mdmx.igen (Maxi, Mini): Rename Max, Min.

	* interp.c (sim_info): Delete.

Fri Feb 27 18:41:01 1998  Doug Evans  <[e-mail]>

	* interp.c (DECLARE_OPTION_HANDLER): Use it.
	(mips_option_handler): New argument `cpu'.
	(sim_open): Update call to sim_add_option_table.

Wed Feb 25 18:56:22 1998  Andrew Cagney  <[e-mail]>

	* mips.igen (CxC1): Add tracing.

Fri Feb 20 17:43:21 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h (Max, Min): Declare.

	* interp.c (Max, Min): New functions.

	* mips.igen (BC1): Add tracing.
	
Thu Feb 19 14:50:00 1998  John Metzler  <[e-mail]>
	
	* interp.c Added memory map for stack in vr4100
	
Thu Feb 19 10:21:21 1998  Gavin Koch  <[e-mail]>

	* interp.c (load_memory): Add missing "break"'s.

Tue Feb 17 12:45:35 1998  Andrew Cagney  <[e-mail]>

	* interp.c (sim_store_register, sim_fetch_register): Pass in
 	length parameter.  Return -1.

Tue Feb 10 11:57:40 1998  Ian Carmichael  <[e-mail]>

	* interp.c: Added hardware init hook, fixed warnings.

Sat Feb  7 17:16:20 1998  Andrew Cagney  <[e-mail]>

	* Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.

Tue Feb  3 11:36:02 1998  Andrew Cagney  <[e-mail]>

	* interp.c (ifetch16): New function.

	* sim-main.h (IMEM32): Rename IMEM.
	(IMEM16_IMMED): Define.
	(IMEM16): Define.
	(DELAY_SLOT): Update.
	
	* m16run.c (sim_engine_run): New file.
	
	* m16.igen: All instructions except LB.
	(LB): Call do_load_byte.
	* mips.igen (do_load_byte): New function.
	(LB): Call do_load_byte.

	* mips.igen: Move spec for insn bit size and high bit from here.
	* Makefile.in (tmp-igen, tmp-m16): To here.

	* m16.dc: New file, decode mips16 instructions.

	* Makefile.in (SIM_NO_ALL): Define.
	(tmp-m16): Generate both 16 bit and 32 bit simulator engines.

Tue Feb  3 11:28:00 1998  Andrew Cagney  <[e-mail]>

	* configure.in (mips_fpu_bitsize): For tx39, restrict floating
 	point unit to 32 bit registers.
	* configure: Re-generate.

Sun Feb  1 15:47:14 1998  Andrew Cagney  <[e-mail]>

	* configure.in (sim_use_gen): Make IGEN the default simulator
 	generator for generic 32 and 64 bit mips targets.
	* configure: Re-generate.

Sun Feb  1 16:52:37 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h (SizeFGR): Determine from floating-point and not gpr
 	bitsize.

	* interp.c (sim_fetch_register, sim_store_register): Read/write
 	FGR from correct location.
	(sim_open): Set size of FGR's according to
 	WITH_TARGET_FLOATING_POINT_BITSIZE.
	
	* sim-main.h (FGR): Store floating point registers in a separate
 	array.

Sun Feb  1 16:47:51 1998  Andrew Cagney  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Tue Feb  3 00:10:50 1998  Andrew Cagney  <[e-mail]>

	* interp.c (ColdReset): Call PENDING_INVALIDATE.

	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.

	* interp.c (pending_tick): New function.  Deliver pending writes.

	* sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
 	PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
 	it can handle mixed sized quantites and single bits.
	
Mon Feb  2 17:43:15 1998  Andrew Cagney  <[e-mail]>

	* interp.c (oengine.h): Do not include when building with IGEN.
	(sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
	(sim_info): Ditto for PROCESSOR_64BIT.
	(sim_monitor): Replace ut_reg with unsigned_word.
	(*): Ditto for t_reg.
	(LOADDRMASK): Define.
	(sim_open): Remove defunct check that host FP is IEEE compliant,
 	using software to emulate floating point.
	(value_fpr, ...): Always compile, was conditional on HASFPU.

Sun Feb  1 11:15:29 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
 	size.

	* interp.c (SD, CPU): Define.
	(mips_option_handler): Set flags in each CPU.
	(interrupt_event): Assume CPU 0 is the one being iterrupted.
	(sim_close): Do not clear STATE, deleted anyway.
	(sim_write, sim_read): Assume CPU zero's vm should be used for
 	data transfers.
	(sim_create_inferior): Set the PC for all processors.
	(sim_monitor, store_word, load_word, mips16_entry): Add cpu
 	argument.
	(mips16_entry): Pass correct nr of args to store_word, load_word.
	(ColdReset): Cold reset all cpu's.
	(signal_exception): Pass cpu to sim_monitor & mips16_entry.
	(sim_monitor, load_memory, store_memory, signal_exception): Use
 	`CPU' instead of STATE_CPU.


	* sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
 	SD or CPU_.
	
	* sim-main.h (signal_exception): Add sim_cpu arg.
	(SignalException*): Pass both SD and CPU to signal_exception.
	* interp.c (signal_exception): Update.
	
	* sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
 	Ditto
	(sync_operation, prefetch, cache_op, store_memory, load_memory,
 	address_translation): Ditto
	(decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
	
Sat Jan 31 18:15:41 1998  Andrew Cagney  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Sat Jan 31 14:49:24 1998  Andrew Cagney  <[e-mail]>

	* interp.c (sim_engine_run): Add `nr_cpus' argument.

	* mips.igen (model): Map processor names onto BFD name.	

	* sim-main.h (CPU_CIA): Delete.
 	(SET_CIA, GET_CIA): Define

Wed Jan 21 16:16:27 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h (GPR_SET): Define, used by igen when zeroing a
 	regiser.

	* configure.in (default_endian): Configure a big-endian simulator
 	by default.
	* configure: Re-generate.
	
Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Mon Jan  5 20:38:54 1998  Mark Alexander  <[e-mail]>

	* interp.c (sim_monitor): Handle Densan monitor outbyte
	and inbyte functions.

1997-12-29  Felix Lee  <[e-mail]>

	* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).

Wed Dec 17 14:48:20 1997  Jeffrey A Law  ([e-mail])

	* Makefile.in (tmp-igen): Arrange for $zero to always be
	reset to zero after every instruction.

Mon Dec 15 23:17:11 1997  Andrew Cagney  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Wed Dec 10 17:10:45 1997  Jeffrey A Law  ([e-mail])

	* mips.igen (MSUB): Fix to work like MADD.
	* gencode.c (MSUB): Similarly.

Thu Dec  4 09:21:05 1997  Doug Evans  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Wed Nov 26 11:00:23 1997  Andrew Cagney  <[e-mail]>

	* mips.igen (LWC1): Correct assembler - lwc1 not swc1.

Sun Nov 23 01:45:20 1997  Andrew Cagney  <[e-mail]>

	* sim-main.h (sim-fpu.h): Include.

	* interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
 	Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
 	using host independant sim_fpu module.

Thu Nov 20 19:56:22 1997  Andrew Cagney  <[e-mail]>

	* interp.c (signal_exception): Report internal errors with SIGABRT
 	not SIGQUIT.

	* sim-main.h (C0_CONFIG): New register.
	(signal.h): No longer include.

	* interp.c (decode_coproc): Allow access C0_CONFIG to register.

Tue Nov 18 15:33:48 1997  Doug Evans  <[e-mail]>

	* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).

Fri Nov 14 11:56:48 1997  Andrew Cagney  <[e-mail]>

	* mips.igen: Tag vr5000 instructions.
	(ANDI): Was missing mipsIV model, fix assembler syntax.
	(do_c_cond_fmt): New function.
	(C.cond.fmt): Handle mips I-III which do not support CC field
 	separatly.
	(bc1): Handle mips IV which do not have a delaed FCC separatly.
	(SDR): Mask paddr when BigEndianMem, not the converse as specified
 	in IV3.2 spec.
	(DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
 	vr5000 which saves LO in a GPR separatly.
	
	* configure.in (enable-sim-igen): For vr5000, select vr5000
 	specific instructions.
	* configure: Re-generate.
	
Wed Nov 12 14:42:52 1997  Andrew Cagney  <[e-mail]>

	* Makefile.in (SIM_OBJS): Add sim-fpu module.

	* interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
 	fmt_uninterpreted_64 bit cases to switch.  Convert to
 	fmt_formatted,

	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,

	* mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
 	as specified in IV3.2 spec.
	(MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.

Tue Nov 11 12:38:23 1997  Andrew Cagney  <[e-mail]>

	* mips.igen: Delay slot branches add OFFSET to NIA not CIA.
 	(MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
	(MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
 	PENDING_FILL versions of instructions.  Simplify.
	(X): New function.
	(MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
 	instructions.
	(BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
 	a signed value.
	(MTHI, MFHI): Disable code checking HI-LO.
	
	* sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
 	global.
	(NULLIFY_NEXT_INSTRUCTION): Call dotrace.

Thu Nov  6 16:36:35 1997  Andrew Cagney  <[e-mail]>

	* gencode.c (build_mips16_operands): Replace IPC with cia.

	* interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
 	value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
 	IPC to `cia'.
	(UndefinedResult): Replace function with macro/function
 	combination.
	(sim_engine_run): Don't save PC in IPC.

	* sim-main.h (IPC): Delete.


	* interp.c (signal_exception, store_word, load_word,
 	address_translation, load_memory, store_memory, cache_op,
 	prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
 	cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
 	current instruction address - cia - argument.
	(sim_read, sim_write): Call address_translation directly.
	(sim_engine_run): Rename variable vaddr to cia.
	(signal_exception): Pass cia to sim_monitor
	
	* sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
 	Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
 	COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.

	* sim-main.h (SignalExceptionSimulatorFault): Delete definition.
  	* interp.c (sim_open): Replace SignalExceptionSimulatorFault with
 	SIM_ASSERT.
	
	* interp.c (signal_exception): Pass restart address to
 	sim_engine_restart.

	* Makefile.in (semantics.o, engine.o, support.o, itable.o,
 	idecode.o): Add dependency.

	* sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
 	Delete definitions
	(DELAY_SLOT): Update NIA not PC with branch address.
	(NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.

	* mips.igen: Use CIA not PC in branch calculations.
	(illegal): Call SignalException.
 	(BEQ, ADDIU): Fix assembler.

Wed Nov  5 12:19:56 1997  Andrew Cagney  <[e-mail]>

	* m16.igen (JALX): Was missing.

	* configure.in (enable-sim-igen): New configuration option.
	* configure: Re-generate.
	
	* sim-main.h (MAX_INSNS, INSN_NAME): Define.

	* interp.c (load_memory, store_memory): Delete parameter RAW.
	(sim_read, sim_write): Use sim_core_{read,write}_buffer directly
 	bypassing {load,store}_memory.

	* sim-main.h (ByteSwapMem): Delete definition.

	* Makefile.in (SIM_OBJS): Add sim-memopt module.

	* interp.c (sim_do_command, sim_commands): Delete mips specific
 	commands.  Handled by module sim-options.
		
	* sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
	(WITH_MODULO_MEMORY): Define.

	* interp.c (sim_info): Delete code printing memory size.

	* interp.c (mips_size): Nee sim_size, delete function.
	(power2): Delete.
	(monitor, monitor_base, monitor_size): Delete global variables.
	(sim_open, sim_close): Delete code creating monitor and other
 	memory regions.  Use sim-memopts module, via sim_do_commandf, to
 	manage memory regions.
	(load_memory, store_memory): Use sim-core for memory model.
	
	* interp.c (