changelog

这个是LINUX下的GDB调度工具的源码

	Reduce unnecessarily high timer event frequency.  
	* dv-tx3904cpu.c: Ditto for interrupt event.
	
Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <[e-mail]>

	* interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 	to allay warnings.
	(interrupt_event): Made non-static.
	
	* dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 	interchange of configuration values for external vs. internal
 	clock dividers.
	
Tue Jun  9 12:46:24 1998  Ian Carmichael  <[e-mail]>

	* mips.igen (BREAK): Moved code to here for 
	simulator-reserved break instructions.
	* gencode.c (build_instruction): Ditto.
	* interp.c (signal_exception): Code moved from here.  Non-
	reserved instructions now use exception vector, rather 
	than halting sim.
	* sim-main.h: Moved magic constants to here.

Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 	register upon non-zero interrupt event level, clear upon zero
 	event value.
	* dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
	by passing zero event value.
	(*_io_{read,write}_buffer): Endianness fixes.
	* dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
	(deliver_*_tick): Reduce sim event interval to 75% of count interval.

	* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
	serial I/O and timer module at base address 0xFFFF0000.
	
Tue Jun  9 11:52:29 1998  Gavin Koch  <[e-mail]>

	* mips.igen (SWC1) : Correct the handling of ReverseEndian 
	and BigEndianCPU.

Tue Jun  9 11:40:57 1998  Gavin Koch  <[e-mail]>

	* configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
	parts.
	* configure: Update.

Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904tmr.c: New file - implements tx3904 timer.
	* dv-tx3904{irc,cpu}.c: Mild reformatting.
	* configure.in: Include tx3904tmr in hw_device list.
	* configure: Rebuilt.
	* interp.c (sim_open): Instantiate three timer instances.
	Fix address typo of tx3904irc instance.

Tue Jun  2 15:48:02 1998  Ian Carmichael  <[e-mail]>

	* interp.c (signal_exception): SystemCall exception now uses
	the exception vector.

Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <[e-mail]>

	* interp.c (decode_coproc): For TX39, add stub COP0 register #3,
	to allay warnings.

Fri May 29 11:40:39 1998  Andrew Cagney  <[e-mail]>

	* configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.

Mon May 25 20:47:45 1998  Andrew Cagney  <[e-mail]>

	* dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.

	* dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 	sim-main.h. Declare a struct hw_descriptor instead of struct
 	hw_device_descriptor.

Mon May 25 12:41:38 1998  Andrew Cagney  <[e-mail]>

	* mips.igen (do_store_left, do_load_left): Compute nr of left and
 	right bits and then re-align left hand bytes to correct byte
 	lanes.  Fix incorrect computation in do_store_left when loading
 	bytes from second word.

Fri May 22 13:34:20 1998  Andrew Cagney  <[e-mail]>

	* configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
	* interp.c (sim_open): Only create a device tree when HW is
 	enabled.

	* dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
	* interp.c (signal_exception): Ditto.

Thu May 21 14:24:11 1998  Gavin Koch  <[e-mail]>

	* gencode.c: Mark BEGEZALL as LIKELY.

Thu May 21 18:57:19 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h (ALU32_END): Sign extend 32 bit results.
	* mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
	
Mon May 18 18:22:42 1998  Frank Ch. Eigler  <[e-mail]>

	* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 	modules.  Recognize TX39 target with "mips*tx39" pattern.
	* configure: Rebuilt.
	* sim-main.h (*): Added many macros defining bits in
 	TX39 control registers.
	(SignalInterrupt): Send actual PC instead of NULL.
	(SignalNMIReset): New exception type.
	* interp.c (board): New variable for future use to identify
	a particular board being simulated.
	(mips_option_handler,mips_options): Added "--board" option.
	(interrupt_event): Send actual PC.
	(sim_open): Make memory layout conditional on board setting.
	(signal_exception): Initial implementation of hardware interrupt
 	handling.  Accept another break instruction variant for simulator
 	exit.
	(decode_coproc): Implement RFE instruction for TX39.
	(mips.igen): Decode RFE instruction as such.
	* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
	* interp.c: Define "jmr3904" and "jmr3904debug" board types and
	bbegin to implement memory map.
	* dv-tx3904cpu.c: New file.
	* dv-tx3904irc.c: New file.

Wed May 13 14:40:11 1998  Gavin Koch  <[e-mail]>

	* mips.igen (check_mt_hilo): Create a separate r3900 version.

Wed May 13 14:11:46 1998  Gavin Koch  <[e-mail]>

	* tx.igen (madd,maddu):  Replace calls to check_op_hilo
	with calls to check_div_hilo.

Wed May 13 09:59:27 1998  Gavin Koch  <[e-mail]>

	* mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
	Replace check_op_hilo with check_mult_hilo and check_div_hilo.
	Add special r3900 version of do_mult_hilo.  
	(do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
	with calls to check_mult_hilo.
	(do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
	with calls to check_div_hilo.

Tue May 12 15:22:11 1998  Andrew Cagney  <[e-mail]>

	* configure.in (SUBTARGET_R3900): Define for mipstx39 target.
  	Document a replacement.

Fri May  8 17:48:19 1998  Ian Carmichael  <[e-mail]>

	* interp.c (sim_monitor): Make mon_printf work.

Wed May  6 19:42:19 1998  Doug Evans  <[e-mail]>

	* sim-main.h (INSN_NAME): New arg `cpu'.

Tue Apr 28 18:33:31 1998  Geoffrey Noer  <[e-mail]>

        * configure: Regenerated to track ../common/aclocal.m4 changes.

Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Sun Apr 26 15:20:01 1998  Tom Tromey  <[e-mail]>

	* acconfig.h: New file.
	* configure.in: Reverted change of Apr 24; use sinclude again.

Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Fri Apr 24 11:19:20 1998  Tom Tromey  <[e-mail]>

	* configure.in: Don't call sinclude.

Fri Apr 24 11:35:01 1998  Andrew Cagney  <[e-mail]>

	* mips.igen (do_store_left): Pass 0 not NULL to store_memory.

Tue Apr 21 11:59:50 1998  Andrew Cagney  <[e-mail]>

	* mips.igen (ERET): Implement.

	* interp.c (decode_coproc): Return sign-extended EPC.

	* mips.igen (ANDI, LUI, MFC0): Add tracing code.

	* interp.c (signal_exception): Do not ignore Trap.
	(signal_exception): On TRAP, restart at exception address.
	(HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
	(signal_exception): Update.
	(sim_open): Patch V_COMMON interrupt vector with an abort sequence
 	so that TRAP instructions are caught.

Mon Apr 20 11:26:55 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h (struct hilo_access, struct hilo_history): Define,
 	contains HI/LO access history.
	(struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
	(HIACCESS, LOACCESS): Delete, replace with
	(HIHISTORY, LOHISTORY): New macros.
	(CHECKHILO): Delete all, moved to mips.igen
	
	* gencode.c (build_instruction): Do not generate checks for
 	correct HI/LO register usage.

	* interp.c (old_engine_run): Delete checks for correct HI/LO
 	register usage.

	* mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 	check_mf_cycles): New functions.
	(do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 	do_divu, domultx, do_mult, do_multu): Use.

	* tx.igen ("madd", "maddu"): Use.
	
Wed Apr 15 18:31:54 1998  Andrew Cagney  <[e-mail]>

	* mips.igen (DSRAV): Use function do_dsrav.
	(SRAV): Use new function do_srav.

	* m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
	(B): Sign extend 11 bit immediate.
	(EXT-B*): Shift 16 bit immediate left by 1.
	(ADDIU*): Don't sign extend immediate value.

Wed Apr 15 10:32:15 1998  Andrew Cagney  <[e-mail]>

	* m16run.c (sim_engine_run): Restore CIA after handling an event.

	* sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 	functions.

	* mips.igen (delayslot32, nullify_next_insn): New functions.
	(m16.igen): Always include.
	(do_*): Add more tracing.

	* m16.igen (delayslot16): Add NIA argument, could be called by a
 	32 bit MIPS16 instruction.
	
	* interp.c (ifetch16): Move function from here.
	* sim-main.c (ifetch16): To here.
	
	* sim-main.c (ifetch16, ifetch32): Update to match current
 	implementations of LH, LW.
	(signal_exception): Don't print out incorrect hex value of illegal
 	instruction.

Wed Apr 15 00:17:25 1998  Andrew Cagney  <[e-mail]>

	* m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 	instruction.

	* m16.igen: Implement MIPS16 instructions.
	
	* mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 	do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 	do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 	do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 	do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 	bodies of corresponding code from 32 bit insn to these.  Also used
 	by MIPS16 versions of functions.
	
	* sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
	(IMEM16): Drop NR argument from macro.

Sat Apr  4 22:39:50 1998  Andrew Cagney  <[e-mail]>

	* Makefile.in (SIM_OBJS): Add sim-main.o.

	* sim-main.h (address_translation, load_memory, store_memory,
 	cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 	as INLINE_SIM_MAIN.
	(pr_addr, pr_uword64): Declare.
	(sim-main.c): Include when H_REVEALS_MODULE_P.
	
	* interp.c (address_translation, load_memory, store_memory,
 	cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 	from here.
	* sim-main.c: To here. Fix compilation problems.
	
	* configure.in: Enable inlining.
	* configure: Re-config.

Sat Apr  4 20:36:25 1998  Andrew Cagney  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Fri Apr  3 04:32:35 1998  Andrew Cagney  <[e-mail]>

	* mips.igen: Include tx.igen.
	* Makefile.in (IGEN_INCLUDE): Add tx.igen.
	* tx.igen: New file, contains MADD and MADDU.

	* interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 	the hardwired constant `7'.
	(store_memory): Ditto.
	(LOADDRMASK): Move definition to sim-main.h.

	mips.igen (MTC0): Enable for r3900.
	(ADDU): Add trace.

	mips.igen (do_load_byte): Delete.
	(do_load, do_store, do_load_left, do_load_write, do_store_left,
 	do_store_right): New functions.
	(SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.

	configure.in: Let the tx39 use igen again.
	configure: Update.
	
Thu Apr  2 10:59:39 1998  Andrew Cagney  <[e-mail]>

	* interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 	not an address sized quantity.  Return zero for cache sizes.

Wed Apr  1 23:47:53 1998  Andrew Cagney  <[e-mail]>

	* mips.igen (r3900): r3900 does not support 64 bit integer
 	operations.

Mon Mar 30 14:46:05 1998  Gavin Koch  <[e-mail]>

	* configure.in (mipstx39*-*-*): Use gencode simulator rather
	than igen one.
	* configure : Rebuild.
	
Fri Mar 27 16:15:52 1998  Andrew Cagney  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Fri Mar 27 15:01:50 1998  Andrew Cagney  <[e-mail]>

	* interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.

Wed Mar 25 16:44:27 1998  Ian Carmichael  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Regenerated to track ../common/aclocal.m4 changes.

Wed Mar 25 12:35:29 1998  Andrew Cagney  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Wed Mar 25 10:05:46 1998  Andrew Cagney  <[e-mail]>

	* interp.c (Max, Min): Comment out functions. Not yet used.

Wed Mar 18 12:38:12 1998  Andrew Cagney  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <[e-mail]>

	* Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 	configurable settings for stand-alone simulator.
	
	* configure.in: Added X11 search, just in case.
	
	* configure: Regenerated.

Wed Mar 11 14:09:10 1998  Andrew Cagney  <[e-mail]>

	* interp.c (sim_write, sim_read, load_memory, store_memory):
 	Replace sim_core_*_map with read_map, write_map, exec_map resp.

Tue Mar  3 13:58:43 1998  Andrew Cagney  <[e-mail]>