gencode.c

这个是LINUX下的GDB调度工具的源码

    "L (0);",
  },
  { "n", "", "mov.l @(<disp>,PC),<REG_N>", "1101nnnni8p4....",
    "MA (1);",
    "R[n] = RLAT ((PH2T (PC) & ~3) + 4 + i);",
    "L (n);",
  },
  { "n", "m", "mov.l @(<disp>,<REG_M>),<REG_N>", "0101nnnnmmmmi4*4",
    "MA (1);",
    "R[n] = RLAT (i + R[m]);",
    "L (n);",
  },
  { "n", "m0", "mov.l @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1110",
    "MA (1);",
    "R[n] = RLAT (R0 + R[m]);",
    "L (n);",
  },
  { "nm", "m", "mov.l @<REG_M>+,<REG_N>", "0110nnnnmmmm0110",
    "MA (1);",
    "R[n] = RLAT (R[m]);",
    "R[m] += 4;",
    "L (n);",
  },
  { "0n", "n", "mov.l @-<REG_N>,R0", "0100nnnn11101011",
    "MA (1);",
    "R[n] -= 4;",
    "R0 = RLAT (R[n]);",
    "L (0);",
  },
  { "n", "m", "mov.l @<REG_M>,<REG_N>", "0110nnnnmmmm0010",
    "MA (1);",
    "R[n] = RLAT (R[m]);",
    "L (n);",
  },
  { "", "0", "mov.l R0,@(<disp>,GBR)", "11000010i8*4....",
    "MA (1);",
    "WLAT (i + GBR, R0);",
  },
  { "", "nm", "mov.l <REG_M>,@(<disp>,<REG_N>)", "0001nnnnmmmmi4*4",
    "MA (1);",
    "WLAT (i + R[n], R[m]);",
  },
  { "", "nm0", "mov.l <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0110",
    "MA (1);",
    "WLAT (R0 + R[n], R[m]);",
  },
  { "n", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
    "MA (1) ;",
    "R[n] -= 4;",
    "WLAT (R[n], R[m]);",
  },
  { "n", "n0", "mov.l R0,@<REG_N>+", "0100nnnn10101011",
    "MA (1) ;",
    "WLAT (R[n], R0);",
    "R[n] += 4;",
  },
  { "", "nm", "mov.l <REG_M>,@<REG_N>", "0010nnnnmmmm0010",
    "MA (1);",
    "WLAT (R[n], R[m]);",
  },

  { "0", "", "mov.w @(<disp>,GBR),R0", "11000101i8*2....",
    "MA (1);",
    "R0 = RSWAT (i + GBR);",
    "L (0);",
  },
  { "n", "", "mov.w @(<disp>,PC),<REG_N>", "1001nnnni8p2....",
    "MA (1);",
    "R[n] = RSWAT (PH2T (PC + 4 + i));",
    "L (n);",
  },
  { "0", "m", "mov.w @(<disp>,<REG_M>),R0", "10000101mmmmi4*2",
    "MA (1);",
    "R0 = RSWAT (i + R[m]);",
    "L (0);",
  },
  { "n", "m0", "mov.w @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1101",
    "MA (1);",
    "R[n] = RSWAT (R0 + R[m]);",
    "L (n);",
  },
  { "nm", "n", "mov.w @<REG_M>+,<REG_N>", "0110nnnnmmmm0101",
    "MA (1);",
    "R[n] = RSWAT (R[m]);",
    "R[m] += 2;",
    "L (n);",
  },
  { "0n", "n", "mov.w @-<REG_N>,R0", "0100nnnn11011011",
    "MA (1);",
    "R[n] -= 2;",
    "R0 = RSWAT (R[n]);",
    "L (0);",
  },
  { "n", "m", "mov.w @<REG_M>,<REG_N>", "0110nnnnmmmm0001",
    "MA (1);",
    "R[n] = RSWAT (R[m]);",
    "L (n);",
  },
  { "", "0", "mov.w R0,@(<disp>,GBR)", "11000001i8*2....",
    "MA (1);",
    "WWAT (i + GBR, R0);",
  },
  { "", "0m", "mov.w R0,@(<disp>,<REG_M>)", "10000001mmmmi4*2",
    "MA (1);",
    "WWAT (i + R[m], R0);",
  },
  { "", "m0n", "mov.w <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0101",
    "MA (1);",
    "WWAT (R0 + R[n], R[m]);",
  },
  { "n", "mn", "mov.w <REG_M>,@-<REG_N>", "0010nnnnmmmm0101",
    "MA (1);",
    "R[n] -= 2;",
    "WWAT (R[n], R[m]);",
  },
  { "n", "0n", "mov.w R0,@<REG_N>+", "0100nnnn10011011",
    "MA (1);",
    "WWAT (R[n], R0);",
    "R[n] += 2;",
  },
  { "", "nm", "mov.w <REG_M>,@<REG_N>", "0010nnnnmmmm0001",
    "MA (1);",
    "WWAT (R[n], R[m]);",
  },

  { "0", "", "mova @(<disp>,PC),R0", "11000111i8p4....",
    "R0 = ((i + 4 + PH2T (PC)) & ~0x3);",
  },

  { "", "n0", "movca.l R0, @<REG_N>", "0000nnnn11000011",
    "/* We don't simulate cache, so this insn is identical to mov.  */",
    "MA (1);",
    "WLAT (R[n], R[0]);",
  },

  { "", "n0", "movco.l R0, @<REG_N>", "0000nnnn01110011", 
    "/* LDST -> T */",
    "SET_SR_T (LDST);",
    "/* if (T) R0 -> (Rn) */",
    "if (T)",
    "  WLAT (R[n], R[0]);",
    "/* 0 -> LDST */",
    "SET_LDST (0);",
  },

  { "0", "n", "movli.l @<REG_N>, R0", "0000nnnn01100011", 
    "/* 1 -> LDST */",
    "SET_LDST (1);",
    "/* (Rn) -> R0 */",
    "R[0] = RLAT (R[n]);",
    "/* if (interrupt/exception) 0 -> LDST */",
    "/* (we don't simulate asynchronous interrupts/exceptions) */",
  },

  { "n", "", "movt <REG_N>", "0000nnnn00101001",
    "R[n] = T;",
  },
  { "", "", "movrt <REG_N>", "0000nnnn00111001",
    "R[n] = (T == 0);",	
  },
  { "0", "n", "movua.l @<REG_N>,R0", "0100nnnn10101001",
    "int regn = R[n];",
    "int e = target_little_endian ? 3 : 0;",
    "MA (1);",
    "R[0] = (RBAT (regn + (0^e)) << 24) + (RBAT (regn + (1^e)) << 16) + ",
    "  (RBAT (regn + (2^e)) << 8) + RBAT (regn + (3^e));",
    "L (0);",
  },
  { "0n", "n", "movua.l @<REG_N>+,R0", "0100nnnn11101001",
    "int regn = R[n];",
    "int e = target_little_endian ? 3 : 0;",
    "MA (1);",
    "R[0] = (RBAT (regn + (0^e)) << 24) + (RBAT (regn + (1^e)) << 16) + ",
    "  (RBAT (regn + (2^e)) << 8) + RBAT (regn + (3^e));",
    "R[n] += 4;",
    "L (0);",
  },
  { "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
    "MACL = ((int) R[n]) * ((int) R[m]);",
  },
#if 0  /* FIXME: The above cast to int is not really portable.
	  It should be replaced by a SEXT32 macro.  */
  { "", "nm", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
    "MACL = R[n] * R[m];",
  },
#endif

  /* muls.w - see muls */
  { "", "mn", "muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
    "MACL = ((int) (short) R[n]) * ((int) (short) R[m]);",
  },

  /* mulu.w - see mulu */
  { "", "mn", "mulu <REG_M>,<REG_N>", "0010nnnnmmmm1110",
    "MACL = (((unsigned int) (unsigned short) R[n])",
    "        * ((unsigned int) (unsigned short) R[m]));",
  },

  { "n", "m", "neg <REG_M>,<REG_N>", "0110nnnnmmmm1011",
    "R[n] = - R[m];",
  },

  { "n", "m", "negc <REG_M>,<REG_N>", "0110nnnnmmmm1010",
    "ult = -T;",
    "SET_SR_T (ult > 0);",
    "R[n] = ult - R[m];",
    "SET_SR_T (T || (R[n] > ult));",
  },

  { "", "", "nop", "0000000000001001",
    "/* nop */",
  },

  { "n", "m", "not <REG_M>,<REG_N>", "0110nnnnmmmm0111",
    "R[n] = ~R[m];",
  },

  /* sh4a */
  { "", "n", "icbi @<REG_N>", "0000nnnn11100011",
    "/* Except for the effect on the cache - which is not simulated -",
    "   this is like a nop.  */",
  },

  { "", "n", "ocbi @<REG_N>", "0000nnnn10010011",
    "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop.  */",
    "/* FIXME: Cache not implemented */",
  },

  { "", "n", "ocbp @<REG_N>", "0000nnnn10100011",
    "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop.  */",
    "/* FIXME: Cache not implemented */",
  },

  { "", "n", "ocbwb @<REG_N>", "0000nnnn10110011",
    "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop.  */",
    "/* FIXME: Cache not implemented */",
  },

  { "0", "", "or #<imm>,R0", "11001011i8*1....",
    "R0 |= i;",
  },
  { "n", "m", "or <REG_M>,<REG_N>", "0010nnnnmmmm1011",
    "R[n] |= R[m];",
  },
  { "", "0", "or.b #<imm>,@(R0,GBR)", "11001111i8*1....",
    "MA (1);",
    "WBAT (R0 + GBR, (RBAT (R0 + GBR) | i));",
  },

  { "", "n", "pref @<REG_N>", "0000nnnn10000011",
    "/* Except for the effect on the cache - which is not simulated -",
    "   this is like a nop.  */",
  },

  /* sh4a */
  { "", "n", "prefi @<REG_N>", "0000nnnn11010011",
    "/* Except for the effect on the cache - which is not simulated -",
    "   this is like a nop.  */",
  },

  /* sh4a */
  { "", "", "synco", "0000000010101011", 
    "/* Except for the effect on the pipeline - which is not simulated -", 
    "   this is like a nop.  */",
  },

  { "n", "n", "rotcl <REG_N>", "0100nnnn00100100",
    "ult = R[n] < 0;",
    "R[n] = (R[n] << 1) | T;",
    "SET_SR_T (ult);",
  },

  { "n", "n", "rotcr <REG_N>", "0100nnnn00100101",
    "ult = R[n] & 1;",
    "R[n] = (UR[n] >> 1) | (T << 31);",
    "SET_SR_T (ult);",
  },

  { "n", "n", "rotl <REG_N>", "0100nnnn00000100",
    "SET_SR_T (R[n] < 0);",
    "R[n] <<= 1;",
    "R[n] |= T;",
  },

  { "n", "n", "rotr <REG_N>", "0100nnnn00000101",
    "SET_SR_T (R[n] & 1);",
    "R[n] = UR[n] >> 1;",
    "R[n] |= (T << 31);",
  },

  { "", "", "rte", "0000000000101011", 
#if 0
    /* SH-[12] */
    "int tmp = PC;",
    "SET_NIP (PT2H (RLAT (R[15]) + 2));",
    "R[15] += 4;",
    "SET_SR (RLAT (R[15]) & 0x3f3);",
    "R[15] += 4;",
    "Delay_Slot (PC + 2);",
#else
    "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
    "SET_SR (SSR);",
    "SET_NIP (PT2H (SPC));",
    "cycles += 2;",
    "Delay_Slot (PC + 2);",
#endif
  },

  { "", "", "rts", "0000000000001011",
    "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
    "SET_NIP (PT2H (PR));",
    "cycles += 2;",
    "Delay_Slot (PC + 2);",
  },
  { "", "", "rts/n", "0000000001101011",
    "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
    "SET_NIP (PT2H (PR));",
  },
  { "0", "n", "rtv/n <REG_N>", "0000nnnn01111011",
    "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
    "R0 = R[n];",
    "L (0);",
    "SET_NIP (PT2H (PR));",
  },

  /* sh4a */
  { "", "", "setdmx", "0000000010011000",
    "saved_state.asregs.cregs.named.sr |=  SR_MASK_DMX;"
    "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMY;"
  },

  /* sh4a */
  { "", "", "setdmy", "0000000011001000",
    "saved_state.asregs.cregs.named.sr |=  SR_MASK_DMY;"
    "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMX;"
  },

  /* sh-dsp */
  { "", "n", "setrc <REG_N>", "0100nnnn00010100",
    "SET_RC (R[n]);",
  },
  { "", "", "setrc #<imm>", "10000010i8*1....",
    /* It would be more realistic to let loop_start point to some static
       memory that contains an illegal opcode and then give a bus error when
       the loop is eventually encountered, but it seems not only simpler,
       but also more debugging-friendly to just catch the failure here.  */
    "if (BUSERROR (RS | RE, maskw))",
    "  RAISE_EXCEPTION (SIGILL);",
    "else {",
    "  SET_RC (i);",
    "  loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);",
    "  CHECK_INSN_PTR (insn_ptr);",
    "}",
  },

  { "", "", "sets", "0000000001011000",
    "SET_SR_S (1);",
  },

  { "", "", "sett", "0000000000011000",
    "SET_SR_T (1);",
  },

  { "n", "mn", "shad <REG_M>,<REG_N>", "0100nnnnmmmm1100",
    "R[n] = (R[m] < 0) ? (R[m]&0x1f ? R[n] >> ((-R[m])&0x1f) : R[n] >> 31) : (R[n] << (R[m] & 0x1f));",
  },

  { "n", "n", "shal <REG_N>", "0100nnnn00100000",
    "SET_SR_T (R[n] < 0);",
    "R[n] <<= 1;",
  },

  { "n", "n", "shar <REG_N>", "0100nnnn00100001",
    "SET_SR_T (R[n] & 1);",
    "R[n] = R[n] >> 1;",
  },

  { "n", "mn", "shld <REG_M>,<REG_N>", "0100nnnnmmmm1101",
    "R[n] = (R[m] < 0) ? (R[m]&0x1f ? UR[n] >> ((-R[m])&0x1f) : 0): (R[n] << (R[m] & 0x1f));",
  },

  { "n", "n", "shll <REG_N>", "0100nnnn00000000",
    "SET_SR_T (R[n] < 0);",
    "R[n] <<= 1;",
  },

  { "n", "n", "shll2 <REG_N>", "0100nnnn00001000",
    "R[n] <<= 2;",
  },
  { "n", "n", "shll8 <REG_N>", "0100nnnn00011000",
    "R[n] <<= 8;",
  },
  { "n", "n", "shll16 <REG_N>", "0100nnnn00101000",
    "R[n] <<= 16;",
  },

  { "n", "n", "shlr <REG_N>", "0100nnnn00000001",
    "SET_SR_T (R[n] & 1);",
    "R[n] = UR[n] >> 1;",
  },

  { "n", "n", "shlr2 <REG_N>", "0100nnnn00001001",
    "R[n] = UR[n] >> 2;",
  },
  { "n", "n", "shlr8 <REG_N>", "0100nnnn00011001",
    "R[n] = UR[n] >> 8;",
  },
  { "n", "n", "shlr16 <REG_N>", "0100nnnn00101001",
    "R[n] = UR[n] >> 16;",
  },

  { "", "", "sleep", "0000000000011011",
    "nip += trap (0xc3, &R0, PC, memory, maskl, maskw, endianw);",
  },

  { "n", "", "stc <CREG_M>,<REG_N>", "0000nnnnmmmm0010",
    "R[n] = CREG (m);",
  },

  { "n", "", "stc SGR,<REG_N>", "0000nnnn00111010",
    "if (SR_MD)",
    "  R[n] = SGR; /* priv mode */",
    "else",
    "  RAISE_EXCEPTION (SIGILL); /* user mode */",
  },
  { "n", "", "stc DBR,<REG_N>", "0000nnnn11111010",
    "if (SR_MD)",
    "  R[n] = DBR; /* priv mode */",
    "else",
    "  RAISE_EXCEPTION (SIGILL); /* user mode */",
  },
  { "n", "", "stc TBR,<REG_N>", "0000nnnn01001010",
    "if (SR_MD)",	/* FIXME? */
    "  R[n] = TBR; /* priv mode */",
    "else",
    "  RAISE_EXCEPTION (SIGILL); /* user mode */",
  },
  { "n", "n", "stc.l <CREG_M>,@-<REG_N>", "0100nnnnmmmm0011",
    "MA (1);",
    "R[n] -= 4;",
    "WLAT (R[n], CREG (m));",
  },
  { "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010",
    "if (SR_MD)",
    "{ /* priv mode */",
    "  MA (1);",
    "  R[n] -= 4;",
    "  WLAT (R[n], SGR);",
    "}",
    "else",
    "  RAISE_EXCEPTION (SIGILL); /* user mode */",
  },
  { "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010",
    "if (SR_MD)",
    "{ /* priv mode */",
    "  MA (1);",
    "  R[n] -= 4;",
    "  WLAT (R[n], DBR);",
    "}",
    "else",
    "  RAISE_EXCEPTION (SIGILL); /* user mode */",
  },

  { "n", "", "sts <SREG_M>,<REG_N>", "0000nnnnssss1010",
    "R[n] = SREG (m);",
  },
  { "n", "n", "sts.l <SREG_M>,@-<REG_N>", "0100nnnnssss0010",
    "MA (1);",
    "R[n] -= 4;",
    "WLAT (R[n], SREG (m));",
  },

  { "n", "nm", "sub <REG_M>,<REG_N>", "0011nnnnmmmm1000",
    "R[n] -= R[m];",
  },

  { "n", "nm", "subc <REG_M>,<REG_N>", "0011nnnnmmmm1010",
    "ult = R[n] - T;",
    "SET_SR_T (ult > R[n]);",
    "R[n] = ult - R[m];",
    "SET_SR_T (T || (R[n] > ult));",
  },

  { "n", "nm", "subv <REG_M>,<REG_N>", "0011nnnnmmmm1011",
    "ult = R[n] - R[m];",
    "SET_SR_T (((R[n] ^ R[m]) & (ult ^ R[n])) >> 31);",
    "R[n] = ult;",
  },

  { "n", "nm", "swap.b <REG_M>,<REG_N>", "0110nnnnmmmm1000",
    "R[n] = ((R[m] & 0xffff0000)",
    "        | ((R[m] << 8) & 0xff00)",
    "        | ((R[m] >> 8) & 0x00ff));",
  },