interp.c

这个是LINUX下的GDB调度工具的源码

    case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
    case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
    case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
    case SIM_SH_FR15_REGNUM:
      SET_FI (rn - SIM_SH_FR0_REGNUM, val);
      break;
    case SIM_SH_DSR_REGNUM:
      DSR = val;
      break;
    case SIM_SH_A0G_REGNUM:
      A0G = val;
      break;
    case SIM_SH_A0_REGNUM:
      A0 = val;
      break;
    case SIM_SH_A1G_REGNUM:
      A1G = val;
      break;
    case SIM_SH_A1_REGNUM:
      A1 = val;
      break;
    case SIM_SH_M0_REGNUM:
      M0 = val;
      break;
    case SIM_SH_M1_REGNUM:
      M1 = val;
      break;
    case SIM_SH_X0_REGNUM:
      X0 = val;
      break;
    case SIM_SH_X1_REGNUM:
      X1 = val;
      break;
    case SIM_SH_Y0_REGNUM:
      Y0 = val;
      break;
    case SIM_SH_Y1_REGNUM:
      Y1 = val;
      break;
    case SIM_SH_MOD_REGNUM:
      SET_MOD (val);
      break;
    case SIM_SH_RS_REGNUM:
      RS = val;
      break;
    case SIM_SH_RE_REGNUM:
      RE = val;
      break;
    case SIM_SH_SSR_REGNUM:
      SSR = val;
      break;
    case SIM_SH_SPC_REGNUM:
      SPC = val;
      break;
    /* The rn_bank idiosyncracies are not due to hardware differences, but to
       a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
    case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
    case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
    case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
    case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
      if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
	{
	  rn -= SIM_SH_R0_BANK0_REGNUM;
	  saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val;
	}
      else
      if (SR_MD && SR_RB)
	Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val;
      else
	saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val;
      break;
    case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
    case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
    case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
    case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
      if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
	{
	  rn -= SIM_SH_R0_BANK1_REGNUM;
	  saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val;
	}
      else
      if (SR_MD && SR_RB)
	saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
      else
	Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val;
      break;
    case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
    case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
    case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
    case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
      SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val);
      break;
    case SIM_SH_TBR_REGNUM:
      TBR = val;
      break;
    case SIM_SH_IBNR_REGNUM:
      IBNR = val;
      break;
    case SIM_SH_IBCR_REGNUM:
      IBCR = val;
      break;
    case SIM_SH_BANK_REGNUM:
      /* This is a pseudo-register maintained just for gdb.
	 It tells us what register bank gdb would like to read/write.  */
      gdb_bank_number = val;
      break;
    case SIM_SH_BANK_MACL_REGNUM:
      saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val;
      break;
    case SIM_SH_BANK_GBR_REGNUM:
      saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val;
      break;
    case SIM_SH_BANK_PR_REGNUM:
      saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val;
      break;
    case SIM_SH_BANK_IVN_REGNUM:
      saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val;
      break;
    case SIM_SH_BANK_MACH_REGNUM:
      saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val;
      break;
    default:
      return 0;
    }
  return -1;
}

int
sim_fetch_register (sd, rn, memory, length)
     SIM_DESC sd;
     int rn;
     unsigned char *memory;
     int length;
{
  int val;

  init_pointers ();
  switch (rn)
    {
    case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
    case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
    case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
    case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
    case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
    case SIM_SH_R15_REGNUM:
      val = saved_state.asregs.regs[rn];
      break;
    case SIM_SH_PC_REGNUM:
      val = saved_state.asregs.pc;
      break;
    case SIM_SH_PR_REGNUM:
      val = PR;
      break;
    case SIM_SH_GBR_REGNUM:
      val = GBR;
      break;
    case SIM_SH_VBR_REGNUM:
      val = VBR;
      break;
    case SIM_SH_MACH_REGNUM:
      val = MACH;
      break;
    case SIM_SH_MACL_REGNUM:
      val = MACL;
      break;
    case SIM_SH_SR_REGNUM:
      val = GET_SR ();
      break;
    case SIM_SH_FPUL_REGNUM:
      val = FPUL;
      break;
    case SIM_SH_FPSCR_REGNUM:
      val = GET_FPSCR ();
      break;
    case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
    case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
    case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
    case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
    case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
    case SIM_SH_FR15_REGNUM:
      val = FI (rn - SIM_SH_FR0_REGNUM);
      break;
    case SIM_SH_DSR_REGNUM:
      val = DSR;
      break;
    case SIM_SH_A0G_REGNUM:
      val = SEXT (A0G);
      break;
    case SIM_SH_A0_REGNUM:
      val = A0;
      break;
    case SIM_SH_A1G_REGNUM:
      val = SEXT (A1G);
      break;
    case SIM_SH_A1_REGNUM:
      val = A1;
      break;
    case SIM_SH_M0_REGNUM:
      val = M0;
      break;
    case SIM_SH_M1_REGNUM:
      val = M1;
      break;
    case SIM_SH_X0_REGNUM:
      val = X0;
      break;
    case SIM_SH_X1_REGNUM:
      val = X1;
      break;
    case SIM_SH_Y0_REGNUM:
      val = Y0;
      break;
    case SIM_SH_Y1_REGNUM:
      val = Y1;
      break;
    case SIM_SH_MOD_REGNUM:
      val = MOD;
      break;
    case SIM_SH_RS_REGNUM:
      val = RS;
      break;
    case SIM_SH_RE_REGNUM:
      val = RE;
      break;
    case SIM_SH_SSR_REGNUM:
      val = SSR;
      break;
    case SIM_SH_SPC_REGNUM:
      val = SPC;
      break;
    /* The rn_bank idiosyncracies are not due to hardware differences, but to
       a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
    case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
    case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
    case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
    case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
      if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
	{
	  rn -= SIM_SH_R0_BANK0_REGNUM;
	  val = saved_state.asregs.regstack[gdb_bank_number].regs[rn];
	}
      else
      val = (SR_MD && SR_RB
	     ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM)
	     : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
      break;
    case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
    case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
    case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
    case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
      if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
	{
	  rn -= SIM_SH_R0_BANK1_REGNUM;
	  val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8];
	}
      else
      val = (! SR_MD || ! SR_RB
	     ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM)
	     : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
      break;
    case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
    case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
    case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
    case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
      val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM);
      break;
    case SIM_SH_TBR_REGNUM:
      val = TBR;
      break;
    case SIM_SH_IBNR_REGNUM:
      val = IBNR;
      break;
    case SIM_SH_IBCR_REGNUM:
      val = IBCR;
      break;
    case SIM_SH_BANK_REGNUM:
      /* This is a pseudo-register maintained just for gdb.
	 It tells us what register bank gdb would like to read/write.  */
      val = gdb_bank_number;
      break;
    case SIM_SH_BANK_MACL_REGNUM:
      val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL];
      break;
    case SIM_SH_BANK_GBR_REGNUM:
      val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR];
      break;
    case SIM_SH_BANK_PR_REGNUM:
      val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR];
      break;
    case SIM_SH_BANK_IVN_REGNUM:
      val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN];
      break;
    case SIM_SH_BANK_MACH_REGNUM:
      val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH];
      break;
    default:
      return 0;
    }
  * (int *) memory = swap (val);
  return -1;
}

int
sim_trace (sd)
     SIM_DESC sd;
{
  tracing = 1;
  sim_resume (sd, 0, 0);
  tracing = 0;
  return 1;
}

void
sim_stop_reason (sd, reason, sigrc)
     SIM_DESC sd;
     enum sim_stop *reason;
     int *sigrc;
{
  /* The SH simulator uses SIGQUIT to indicate that the program has
     exited, so we must check for it here and translate it to exit.  */
  if (saved_state.asregs.exception == SIGQUIT)
    {
      *reason = sim_exited;
      *sigrc = saved_state.asregs.regs[5];
    }
  else
    {
      *reason = sim_stopped;
      *sigrc = saved_state.asregs.exception;
    }
}

void
sim_info (sd, verbose)
     SIM_DESC sd;
     int verbose;
{
  double timetaken = 
    (double) saved_state.asregs.ticks / (double) now_persec ();
  double virttime = saved_state.asregs.cycles / 36.0e6;

  callback->printf_filtered (callback, "\n\n# instructions executed  %10d\n", 
			     saved_state.asregs.insts);
  callback->printf_filtered (callback, "# cycles                 %10d\n",
			     saved_state.asregs.cycles);
  callback->printf_filtered (callback, "# pipeline stalls        %10d\n",
			     saved_state.asregs.stalls);
  callback->printf_filtered (callback, "# misaligned load/store  %10d\n",
			     saved_state.asregs.memstalls);
  callback->printf_filtered (callback, "# real time taken        %10.4f\n",
			     timetaken);
  callback->printf_filtered (callback, "# virtual time taken     %10.4f\n",
			     virttime);
  callback->printf_filtered (callback, "# profiling size         %10d\n",
			     sim_profile_size);
  callback->printf_filtered (callback, "# profiling frequency    %10d\n",
			     saved_state.asregs.profile);
  callback->printf_filtered (callback, "# profile maxpc          %10x\n",
			     (1 << sim_profile_size) << PROFILE_SHIFT);

  if (timetaken != 0)
    {
      callback->printf_filtered (callback, "# cycles/second          %10d\n", 
				 (int) (saved_state.asregs.cycles / timetaken));
      callback->printf_filtered (callback, "# simulation ratio       %10.4f\n", 
				 virttime / timetaken);
    }
}

void
sim_set_profile (n)
     int n;
{
  saved_state.asregs.profile = n;
}

void
sim_set_profile_size (n)
     int n;
{
  sim_profile_size = n;
}

SIM_DESC
sim_open (kind, cb, abfd, argv)
     SIM_OPEN_KIND kind;
     host_callback *cb;
     struct bfd *abfd;
     char **argv;
{
  char **p;
  int endian_set = 0;
  int i;
  union
    {
      int i;
      short s[2];
      char c[4];
    }
  mem_word;

  sim_kind = kind;
  myname = argv[0];
  callback = cb;

  for (p = argv + 1; *p != NULL; ++p)
    {
      if (strcmp (*p, "-E") == 0)
	{
	  ++p;
	  if (*p == NULL)
	    {
	      /* FIXME: This doesn't use stderr, but then the rest of the
		 file doesn't either.  */
	      callback->printf_filtered (callback, "Missing argument to `-E'.\n");
	      return 0;
	    }
	  target_little_endian = strcmp (*p, "big") != 0;
          endian_set = 1;
	}
      else if (isdigit (**p))
	parse_and_set_memory_size (*p);
    }

  if (abfd != NULL && ! endian_set)
      target_little_endian = ! bfd_big_endian (abfd);

  if (abfd)
    init_dsp (abfd);

  for (i = 4; (i -= 2) >= 0; )
    mem_word.s[i >> 1] = i;
  global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff;

  for (i = 4; --i >= 0; )
    mem_word.c[i] = i;
  endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff;

  /* fudge our descriptor for now */
  return (SIM_DESC) 1;
}

static void
parse_and_set_memory_size (str)
     char *str;
{
  int n;

  n = strtol (str, NULL, 10);
  if (n > 0 && n <= 24)
    sim_memory_size = n;
  else
    callback->printf_filtered (callback, "Bad memory size %d; must be 1 to 24, inclusive\n", n);
}

void
sim_close (sd, quitting)
     SIM_DESC sd;
     int quitting;
{
  /* nothing to do */
}

SIM_RC
sim_load (sd, prog, abfd, from_tty)
     SIM_DESC sd;
     char *prog;
     bfd *abfd;
     int from_tty;
{
  extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
  bfd *prog_bfd;

  prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
			    sim_kind == SIM_OPEN_DEBUG,
			    0, sim_write);

  /* Set the bfd machine type.  */
  if (prog_bfd)
    saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);
  else if (abfd)
    saved_state.asregs.bfd_mach = bfd_get_mach (abfd);
  else
    saved_state.asregs.bfd_mach = 0;

  if (prog_bfd == NULL)
    return SIM_RC_FAIL;
  if (abfd == NULL)
    bfd_close (prog_bfd);
  return SIM_RC_OK;
}

SIM_RC
sim_create_inferior (sd, prog_bfd, argv, env)
     SIM_DESC sd;
     struct bfd *prog_bfd;
     char **argv;
     char **env;
{
  /* Clear the registers. */
  memset (&saved_state, 0,
	  (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state);

  /* Set the PC.  */
  if (prog_bfd != NULL)
    saved_state.asregs.pc = bfd_get_start_address (prog_bfd);

  /* Set the bfd machine type.  */
  if (prog_bfd != NULL)
    saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);

  /* Record the program's arguments. */
  prog_argv = argv;

  return SIM_RC_OK;
}

void
sim_do_command (sd, cmd)
     SIM_DESC sd;
     char *cmd;
{
  char *sms_cmd = "set-memory-size";
  int cmdsize;

  if (cmd == NULL || *cmd == '\0')
    {
      cmd = "help";
    }

  cmdsize = strlen (sms_cmd);
  if (strncmp (cmd, sms_cmd, cmdsize) == 0 
      && strchr (" \t", cmd[cmdsize]) != NULL)
    {
      parse_and_set_memory_size (cmd + cmdsize + 1);
    }
  else if (strcmp (cmd, "help") == 0)
    {
      (callback->printf_filtered) (callback, 
				   "List of SH simulator commands:\n\n");
      (callback->printf_filtered) (callback, "set-memory-size <n> -- Set the number of address bits to use\n");
      (callback->printf_filtered) (callback, "\n");
    }
  else