📄 i386.h
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{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },#if SYSV386_COMPAT/* alias for fsubp */{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },#endif{"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },#if SYSV386_COMPAT{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },#if OLDGCC_COMPAT{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },#endif#else{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },#endif/* subtract reverse */{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },#if SYSV386_COMPAT/* alias for fsubrp */{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },#endif{"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },#if SYSV386_COMPAT{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },#if OLDGCC_COMPAT{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },#endif#else{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },#endif/* multiply */{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },#if SYSV386_COMPAT/* alias for fmulp */{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },#endif{"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },{"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} },{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },/* divide */{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },#if SYSV386_COMPAT/* alias for fdivp */{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },#endif{"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },{"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },#if SYSV386_COMPAT{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },#if OLDGCC_COMPAT{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },#endif#else{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },#endif/* divide reverse */{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },#if SYSV386_COMPAT/* alias for fdivrp */{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },#endif{"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },#if SYSV386_COMPAT{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },#if OLDGCC_COMPAT{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },#endif#else{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },#endif{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} },{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} },{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} },{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} },{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} },{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} },{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} },{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} },{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} },{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} },{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} },{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} },{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} },{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} },{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} },{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} },{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} },{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} },/* processor control */{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} },{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} },{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} },{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} },{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} },{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} },{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} },{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} },{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} },{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} },{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} },/* Short forms of fldenv, fstenv use data size prefix. */{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },/* P6:free st(i), pop st */{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} },#define FWAIT_OPCODE 0x9b{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} },/* Opcode prefixes; we allow them as separate insns too. */#define ADDR_PREFIX_OPCODE 0x67{"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },{"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },{"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },{"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },#define DATA_PREFIX_OPCODE 0x66{"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },{"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },{"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },{"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },#define LOCK_PREFIX_OPCODE 0xf0{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },#define CS_PREFIX_OPCODE 0x2e{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },#define DS_PREFIX_OPCODE 0x3e{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },#define ES_PREFIX_OPCODE 0x26{"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} },#define FS_PREFIX_OPCODE 0x64{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },#define GS_PREFIX_OPCODE 0x65{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },#define SS_PREFIX_OPCODE 0x36{"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} },#define REPNE_PREFIX_OPCODE 0xf2#define REPE_PREFIX_OPCODE 0xf3{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },{"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },{"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },/* 486 extensions. */{"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } },{"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} },{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} },{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} },/* 586 and late 486 extensions. */{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} },/* Pentium extensions. */{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} },{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} },{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} },{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} },/* Pentium II/Pentium Pro extensions. */{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} },{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} },{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} },{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} },{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} },/* official undefined instr. */
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