h8300.h

这个是LINUX下的GDB调度工具的源码

/* Opcode table for the H8/300
   Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2003, 2004
   Free Software Foundation, Inc.
   Written by Steve Chamberlain <[e-mail]>.
   
   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
   
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.
   
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
   
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.  */

/* Instructions are stored as a sequence of nibbles.
   If the nibble has value 15 or less than the representation is complete.
   Otherwise, we record what it contains with several flags.  */

typedef int op_type;

enum h8_flags
{
  L_2  =	0x10,
  L_3  =	0x20,
  /* 3 bit constant, zero not accepted.  */
  L_3NZ =	0x30,
  L_4  =	0x40,
  L_5  =	0x50,
  L_8  =	0x60,
  L_8U =	0x70,
  L_16 =	0x80,
  L_16U =	0x90,
  L_24 =	0xA0,
  L_32 =	0xB0,
  L_P  =	0xC0,

  /* Mask to isolate the L_x size bits.  */
  SIZE =	0xF0,

  REG =		0x0100,
  ABS =		0x0200,
  MEMIND =	0x0300,
  IMM =		0x0400,
  DISP =	0x0500,
  IND =		0x0600,
  POSTINC =	0x0700,
  POSTDEC =	0x0800,
  PREINC =	0x0900,
  PREDEC =	0x0A00,
  PCREL =	0x0B00,
  KBIT =	0x0C00,
  DBIT =	0x0D00,
  CONST_2 =     0x0E00,
  CONST_4 =     0x0F00,
  CONST_8 =     0x1000,
  CONST_16 =    0x1100,
  INDEXB =      0x1200,
  INDEXW =      0x1300,
  INDEXL =      0x1400,
  PCIDXB =      0x1500,
  PCIDXW =      0x1600,
  PCIDXL =      0x1700,
  VECIND =      0x1800,
  LOWREG =      0x1900,
  DATA   =      0x2000,

  /* Synonyms.  */
  INC =		POSTINC,
  DEC =		PREDEC,
  /* Control Registers.  */
  CCR =		0x4000,
  EXR =		0x4100,
  MACH = 	0x4200,
  MACL = 	0x4300,
  RESERV1 = 	0x4400,
  RESERV2 = 	0x4500,
  VBR = 	0x4600,
  SBR = 	0x4700,
  MACREG =	0x4800,
  CCR_EXR = 	0x4900,
  VBR_SBR = 	0x4A00,
  CC_EX_VB_SB =	0x4B00,
  RESERV3 =	0x4C00,
  RESERV4 = 	0x4D00,
  RESERV5 = 	0x4E00,
  RESERV6 = 	0x4F00,

  /* Mask to isolate the addressing mode bits (REG .. PREDEC).  */
  MODE =	0x7F00,

  CTRL = 	0x4000,

  NO_SYMBOLS =  0x8000,
  SRC =		0x10000,
  DST =		0x20000,
  OP3 =		0x40000,
  MEMRELAX = 	0x80000,		/* Move insn which may relax.  */

  DISPREG =	0x100000,
  IGNORE =	0x200000,
  ABSJMP =	0x400000,

  B00 =         0x800000, 		/* Bit 0 must be low.   */
  B01 =         0x1000000, 		/* Bit 0 must be high.  */
  B10 = 	0x2000000, 		/* Bit 1 must be low.   */
  B11 = 	0x4000000, 		/* Bit 1 must be high.  */
  B20 = 	0x8000000, 		/* Bit 2 must be low.   */
  B21 = 	0x10000000, 		/* Bit 2 must be high.  */
  B30 =		0x20000000, 		/* Bit 3 must be low.   */
  B31 =		0x40000000,		/* Bit 3 must be high.  */
  E =  		0x80000000,		/* End of nibble sequence.  */

  /* Immediates smaller than 8 bits are always unsigned.  */
  IMM3 =	IMM | L_3,
  IMM4 =	IMM | L_4,
  IMM5 =	IMM | L_5,
  IMM3NZ =	IMM | L_3NZ,
  IMM2 =	IMM | L_2,

  IMM8 =	IMM | SRC | L_8,
  IMM8U =	IMM | SRC | L_8U,
  IMM16 =	IMM | SRC | L_16,
  IMM16U =	IMM | SRC | L_16U,
  IMM32 =	IMM | SRC | L_32,

  IMM3NZ_NS =   IMM3NZ | NO_SYMBOLS,
  IMM4_NS =	IMM4 | NO_SYMBOLS,
  IMM8U_NS =	IMM8U | NO_SYMBOLS,
  IMM16U_NS =   IMM16U | NO_SYMBOLS,

  RD8  =	DST | L_8  | REG,
  RD16 =	DST | L_16 | REG,
  RD32 =	DST | L_32 | REG,
  R3_8  =       OP3 | L_8  | REG,
  R3_16 =       OP3 | L_16 | REG,
  R3_32 =       OP3 | L_32 | REG,
  RS8  =	SRC | L_8  | REG,
  RS16 =	SRC | L_16 | REG,
  RS32 =	SRC | L_32 | REG,

  RSP =		SRC | L_P | REG,
  RDP =		DST | L_P | REG,

  PCREL8 =	PCREL | L_8,
  PCREL16 =	PCREL | L_16,

  OP3PCREL8 =	OP3 | PCREL | L_8,
  OP3PCREL16 =	OP3 | PCREL | L_16,

  INDEXB16  =	INDEXB | L_16,
  INDEXW16  =	INDEXW | L_16,
  INDEXL16  =	INDEXL | L_16,
  INDEXB16D =	INDEXB | L_16 | DST,
  INDEXW16D =	INDEXW | L_16 | DST,
  INDEXL16D =	INDEXL | L_16 | DST,

  INDEXB32  =	INDEXB | L_32,
  INDEXW32  =	INDEXW | L_32,
  INDEXL32  =	INDEXL | L_32,
  INDEXB32D =	INDEXB | L_32 | DST,
  INDEXW32D =	INDEXW | L_32 | DST,
  INDEXL32D =	INDEXL | L_32 | DST,

  DISP2SRC =	DISP | L_2  | SRC,
  DISP16SRC =	DISP | L_16 | SRC,
  DISP32SRC =	DISP | L_32 | SRC,

  DISP2DST =	DISP | L_2  | DST,
  DISP16DST =	DISP | L_16 | DST,
  DISP32DST =	DISP | L_32 | DST,

  DSTDISPREG =  DST | DISPREG,
  SRCDISPREG =  SRC | DISPREG,

  ABS8SRC  = 	SRC | ABS | L_8,
  ABS16SRC = 	SRC | ABS | L_16U,
  ABS24SRC = 	SRC | ABS | L_24,
  ABS32SRC = 	SRC | ABS | L_32,

  ABS8DST  =	DST | ABS | L_8,
  ABS16DST = 	DST | ABS | L_16U,
  ABS24DST = 	DST | ABS | L_24,
  ABS32DST = 	DST | ABS | L_32,

  ABS8OP3  =	OP3 | ABS | L_8,
  ABS16OP3 = 	OP3 | ABS | L_16U,
  ABS24OP3 = 	OP3 | ABS | L_24,
  ABS32OP3 = 	OP3 | ABS | L_32,

  RDDEC =	DST | DEC,
  RSINC =	SRC | INC,
  RDINC =	DST | INC,