tic4x.h

这个是LINUX下的GDB调度工具的源码

   S  short int immediate     0--15   [A,AB,AY,BI] - -5, 5
   T  integer (C4x)          16--20   [Z] - -5, 12
   U  unsigned integer        0--15   [AU,A3] - 0, 65535
   V  vector (C4x: 0--8)      0--4    [Z] - 25, 7
   W  short int (C4x)         0--7    [T,TC,T2,T2C] - -3, 5
   X  expansion reg (C4x)     0--4    [Z] - IVTP, TVTP
   Y  address reg (C4x)      16--20   [Z] - AR0, DP, SP, IR0
   Z  expansion reg (C4x)    16--20   [Z] - IVTP, TVTP
*/

#define TIC4X_OPERANDS_MAX 7	/* Max number of operands for an inst.  */
#define TIC4X_NAME_MAX 16	/* Max number of chars in parallel name.  */

/* Define the instruction level */
#define OP_C3X   0x1   /* C30 support - supported by all */
#define OP_C4X   0x2   /* C40 support - C40, C44 */
#define OP_ENH   0x4   /* Class LL,LS,M,P,Q,QC enhancements. Argument type
                          I and J is enhanced in these classes - C31>=6.0,
                          C32>=2.0, C33 */
#define OP_LPWR  0x8   /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
                          LC31, C31>=5.0, C32 */
#define OP_IDLE2 0x10  /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
                          C32, C33, C40>=5.0, C44 */

/* The following class definition is a classification scheme for
   putting instructions with similar type of arguments together. It
   simplifies the op-code definitions significantly, as we then only
   need to use the class macroes for 95% of the DSP's opcodes.
*/

/* A: General 2-operand integer operations
   Syntax: <i> src, dst
      src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
      dst = Register (R)
   Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
                SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
                MBn, MHn, MPYSHI, MPYUHI
*/
#define A_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
  { name, opcode|0x00600000, 0xffe00000, "S,R", level }

/* AB: General 2-operand integer operation with condition
   Syntax: <i>c src, dst
       c   = Condition
       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
       dst = Register (R)
   Instr: 1/0 - LDIc
*/
#define AB_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \
  { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \
  { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \
  { name, opcode|0x40600000, 0xf0600000, "S,R", level }

/* AU: General 2-operand unsigned integer operation
   Syntax: <i> src, dst
        src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
        dst = Register (R)
   Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
*/
#define AU_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
  { name, opcode|0x00600000, 0xffe00000, "U,R", level }

/* AF: General 2-operand float to integer operation
   Syntax: <i> src, dst
        src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
        dst = Register (R)
   Instr: 1/0 - FIX
*/
#define AF_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \
  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
  { name, opcode|0x00600000, 0xffe00000, "F,R", level }

/* A2: Limited 1-operand (integer) operation
   Syntax: <i> src
       src = Register (Q), Indirect (*), None
   Instr: 1/0 - NOP
*/
#define A2_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffe00000, "Q", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*", level }, \
  { name, opcode|0x00000000, 0xffe00000, "" , level }

/* A3: General 1-operand unsigned integer operation
   Syntax: <i> src
        src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
   Instr: 1/0 - RPTS
*/
#define A3_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffff0000, "Q", level }, \
  { name, opcode|0x00200000, 0xffff0000, "@", level }, \
  { name, opcode|0x00400000, 0xffff0000, "*", level }, \
  { name, opcode|0x00600000, 0xffff0000, "U", level }

/* A6: Limited 2-operand integer operation
   Syntax: <i> src, dst
       src = Direct (@), Indirect (*)
       dst = Register (R)
   Instr: 1/1 - LDII, C4x: SIGI
*/
#define A6_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,R", level }

/* A7: Limited 2-operand integer store operation
   Syntax: <i> src, dst
       src = Register (R)
       dst = Direct (@), Indirect (*)
   Instr: 2/0 - STI, STII
*/
#define A7_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \
  { name, opcode|0x00400000, 0xffe00000, "R,*", level }

/* AY: General 2-operand signed address load operation
   Syntax: <i> src, dst
        src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
        dst = Address register - ARx, IRx, DP, BK, SP (Y)
   Instr: 0/1 - C4x: LDA
   Note: Q and Y should *never* be the same register
*/
#define AY_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \
  { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \
  { name, opcode|0x00600000, 0xffe00000, "S,Y", level }

/* B: General 2-operand float operation
   Syntax: <i> src, dst
       src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
       dst = Register 0-11 (r)
   Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
                 SUBF, SUBRF, C4x: RSQRF, TOIEEE
*/
#define B_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \
  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
  { name, opcode|0x00600000, 0xffe00000, "F,r", level }

/* BA: General 2-operand integer to float operation
   Syntax: <i> src, dst
       src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
       dst = Register 0-11 (r)
   Instr: 0/1 - C4x: CRCPF
*/
#define BA_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
  { name, opcode|0x00600000, 0xffe00000, "F,r", level }

/* BB: General 2-operand conditional float operation
   Syntax: <i>c src, dst
       c   = Condition
       src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
       dst = Register 0-11 (r)
   Instr: 1/0 - LDFc
*/
#define BB_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \
  { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \
  { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \
  { name, opcode|0x40600000, 0xf0600000, "F,r", level }

/* BI: General 2-operand integer to float operation (yet different to BA)
   Syntax: <i> src, dst
       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
       dst = Register 0-11 (r)
   Instr: 1/0 - FLOAT
*/
#define BI_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
  { name, opcode|0x00600000, 0xffe00000, "S,r", level }

/* B6: Limited 2-operand float operation 
   Syntax: <i> src, dst
       src = Direct (@), Indirect (*)
       dst = Register 0-11 (r)
   Instr: 1/1 - LDFI, C4x: FRIEEE
*/
#define B6_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
  { name, opcode|0x00400000, 0xffe00000, "*,r", level }

/* B7: Limited 2-operand float store operation
   Syntax: <i> src, dst
       src = Register 0-11 (r)
       dst = Direct (@), Indirect (*)
   Instr: 2/0 - STF, STFI
*/
#define B7_CLASS_INSN(name, opcode, level) \
  { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \
  { name, opcode|0x00400000, 0xffe00000, "r,*", level }

/* D: Decrement and brach operations
   Syntax: <i>c ARn, dst
       c   = condition
       ARn = AR register 0-7 (A)
       dst = Register (Q), PC-relative (P)
   Instr: 2/0 - DBc, DBcD
   Alias: <name1> <name2>
*/
#define D_CLASS_INSN(name1, name2, opcode, level) \
  { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
  { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \
  { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
  { name2, opcode|0x02000000, 0xfe200000, "A,P", level }

/* I: General branch operations
   Syntax: <i> dst
       dst = Address (B)
   Instr: 3/1 - BR, BRD, CALL, C4x: LAJ
*/

/* I2: General branch operations (C4x addition)
   Syntax: <i> dst
       dst = Address (B), C4x: Register (Q)
   Instr: 2/0 - RPTB, RPTBD
*/

/* J: General conditional branch operations
   Syntax: <i>c dst
       c   = Condition
       dst = Register (Q), PC-relative (P)
   Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
   Alias: <name1> <name2>
*/
#define J_CLASS_INSN(name1, name2, opcode, level) \
  { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \
  { name1, opcode|0x02000000, 0xffe00000, "P", level }, \
  { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \
  { name2, opcode|0x02000000, 0xffe00000, "P", level }

/* JS: General conditional branch operations
   Syntax: <i>c dst
       c   = Condition
       dst = Register (Q), PC-relative (P)
   Instr: 1/1 - CALLc, C4X: LAJc
*/

/* LL: Load-load parallell operation
   Syntax: <i> src2, dst2 || <i> src1, dst1
       src1 = Indirect 0,1,IR0,IR1 (J)
       dst1 = Register 0-7 (K)
       src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
       dst2 = Register 0-7 (L)
   Instr: 2/0 - LDF||LDF, LDI||LDI
   Alias: i||i, i1||i2, i2||i1
*/
#define LL_CLASS_INSN(name, opcode, level) \
  { name "_"  name    , opcode, 0xfe000000, "i;L|J,K", level }, \
  { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \
  { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level }

/* LS: Store-store parallell operation
   Syntax: <i> src2, dst2 || <i> src1, dst1
       src1 = Register 0-7 (H)
       dst1 = Indirect 0,1,IR0,IR1 (J)
       src2 = Register 0-7 (L)