📄 changelog-9103
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* cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field.2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at> * h8300.h: Comment typo fix.2002-01-03 matthew green <mrg@redhat.com> * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. (PPC_OPCODE_BOOKE64): Likewise.Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) * hppa.h (call, ret): Move to end of table. (addb, addib): PA2.0 variants should have been PA2.0W. (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler happy. (fldw, fldd, fstw, fstd, bb): Likewise. (short loads/stores): Tweak format specifier slightly to keep disassembler happy. (indexed loads/stores): Likewise. (absolute loads/stores): Likewise.2001-12-04 Alexandre Oliva <aoliva@redhat.com> * d10v.h (OPERAND_NOSP): New macro.2001-11-29 Alexandre Oliva <aoliva@redhat.com> * d10v.h (OPERAND_SP): New macro.2001-11-15 Alan Modra <amodra@bigpond.net.au> * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param.2001-11-11 Timothy Wall <twall@alum.mit.edu> * tic54x.h: Revise opcode layout; don't really need a separate structure for parallel opcodes.2001-11-13 Zack Weinberg <zack@codesourcery.com> Alan Modra <amodra@bigpond.net.au> * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to accept WordReg.2001-11-04 Chris Demetriou <cgd@broadcom.com> * mips.h (OPCODE_IS_MEMBER): Remove extra space.2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> * mmix.h: New file.2001-10-18 Chris Demetriou <cgd@broadcom.com> * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end of the expression, to make source code merging easier.2001-10-17 Chris Demetriou <cgd@broadcom.com> * mips.h: Sort coprocessor instruction argument characters in comment, add a few more words of description for "H".2001-10-17 Chris Demetriou <cgd@broadcom.com> * mips.h (INSN_SB1): New cpu-specific instruction bit. (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 if cpu is CPU_SB1.2001-10-17 matthew green <mrg@redhat.com> * ppc.h (PPC_OPCODE_BOOKE64): Fix typo.2001-10-12 matthew green <mrg@redhat.com> * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 instructions, respectively.2001-09-27 Nick Clifton <nickc@cambridge.redhat.com> * v850.h: Remove spurious comment.2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> * h8300.h: Fix compile time warning messages2001-09-04 Richard Henderson <rth@redhat.com> * alpha.h (struct alpha_operand): Pack elements into bitfields.2001-08-31 Eric Christopher <echristo@redhat.com> * mips.h: Remove CPU_MIPS32_4K.2001-08-27 Torbjorn Granlund <tege@swox.com> * ppc.h (PPC_OPERAND_DS): Define.2001-08-25 Andreas Jaeger <aj@suse.de> * d30v.h: Fix declaration of reg_name_cnt. * d10v.h: Fix declaration of d10v_reg_name_cnt. * arc.h: Add prototypes from opcodes/arc-opc.c.2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> * mips.h (INSN_10000): Define. (OPCODE_IS_MEMBER): Check for INSN_10000.2001-08-10 Alan Modra <amodra@one.net.au> * ppc.h: Revert 2001-08-08.2001-08-10 Richard Sandiford <rsandifo@redhat.com> * mips.h (INSN_GP32): Remove. (OPCODE_IS_MEMBER): Remove gp32 parameter. (M_MOVE): New macro identifier.2001-08-08 Alan Modra <amodra@one.net.au> 1999-10-25 Torbjorn Granlund <tege@swox.com> * ppc.h (struct powerpc_operand): New field `reloc'.2001-08-01 Aldy Hernandez <aldyh@redhat.com> * mips.h (INSN_ISA_MASK): Nuke bits 12-15.2001-07-12 Jeff Johnston <jjohnstn@redhat.com> * cgen.h (CGEN_INSN): Add regex support. (build_insn_regex): Declare.2001-07-11 Frank Ch. Eigler <fche@redhat.com> * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. (cgen_cpu_desc): Ditto.2001-07-07 Ben Elliston <bje@redhat.com> * m88k.h: Clean up and reformat. Remove unused code.2001-06-14 Geoffrey Keating <geoffk@redhat.com> * cgen.h (cgen_keyword): Add nonalpha_chars field.2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> * mips.h (CPU_R12000): Define.2001-05-23 John Healy <jhealy@redhat.com> * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> * mips.h (INSN_ISA_MASK): Define.2001-05-12 Alan Modra <amodra@one.net.au> * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg, not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq, and use InvMem as these insns must have register operands.2001-05-04 Alan Modra <amodra@one.net.au> * i386.h (i386_optab): Move InvMem to first operand of pmovmskb and pextrw to swap reg/rm assignments.2001-04-05 Hans-Peter Nilsson <hp@axis.com> * cris.h (enum cris_insn_version_usage): Correct comment for cris_ver_v3p.2001-03-24 Alan Modra <alan@linuxcare.com.au> * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". Add InvMem to first operand of "maskmovdqu".2001-03-22 Hans-Peter Nilsson <hp@axis.com> * cris.h (ADD_PC_INCR_OPCODE): New macro.2001-03-21 Kazu Hirata <kazu@hxi.com> * h8300.h: Fix formatting.2001-03-22 Alan Modra <alan@linuxcare.com.au> * i386.h (i386_optab): Add paddq, psubq.2001-03-19 Alan Modra <alan@linuxcare.com.au> * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define.2001-02-28 Igor Shevlyakov <igor@windriver.com> * m68k.h: new defines for Coldfire V4. Update mcf to know about mcf5407.2001-02-18 lars brinkhoff <lars@nocrew.org> * pdp11.h: New file.2001-02-12 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): SSE integer converison instructions have 64bit versions on x86-64.2001-02-10 Nick Clifton <nickc@redhat.com> * mips.h: Remove extraneous whitespace. Formating change to allow for future contribution.2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> * s390.h: New file.2001-02-02 Patrick Macdonald <patrickm@redhat.com> * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.2001-01-24 Karsten Keil <kkeil@suse.de> * i386.h (i386_optab): Fix swapgs2001-01-14 Alan Modra <alan@linuxcare.com.au> * hppa.h: Describe new '<' and '>' operand types, and tidy existing comments. (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. Remove duplicate "ldw j(s,b),x". Sort some entries.2001-01-13 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Fix pusha and ret templates.2001-01-11 Peter Targett <peter.targett@arccores.com> * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New definitions for masking cpu type. (arc_ext_operand_value) New structure for storing extended operands. (ARC_OPERAND_*) Flags for operand values.2001-01-10 Jan Hubicka <jh@suse.cz> * i386.h (pinsrw): Add. (pshufw): Remove. (cvttpd2dq): Fix operands. (cvttps2dq): Likewise. (movq2q): Rename to movdq2q.2001-01-10 Richard Schaal <richard.schaal@intel.com> * i386.h: Correct movnti instruction.2001-01-09 Jeff Johnston <jjohnstn@redhat.com> * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number of operands (unsigned char or unsigned short). (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.2001-01-05 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Make [sml]fence template to use immext field.2001-01-03 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Fix 64bit pushf template; Add instructions introduced by Pentium42000-12-30 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Add "rex*" instructions; add swapgs; disable jmp/call far direct instructions for 64bit mode; add syscall and sysret; disable registers for 0xc6 template. Add 'q' suffixes to extendable instructions, disable obsolete instructions, add new sign/zero extension ones. (i386_regtab): Add extended registers. (*Suf): Add No_qSuf. (q_Suf, wlq_Suf, bwlq_Suf): New.2000-12-20 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field.2000-12-12 Nick Clifton <nickc@redhat.com> * mips.h: Fix formatting.2000-12-01 Chris Demetriou <cgd@sibyte.com> mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete. (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old OP_*_SYSCALL definitions. (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as 19 bit wait codes. (MIPS operand specifier comments): Remove 'm', add 'U' and 'J', and update the meaning of 'B' so that it's more general. * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5): Renumber, redefine to mean the ISA at which the instruction was added. (INSN_ISA32): New constant. (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32): Renumber to avoid new and/or renumbered INSN_* constants. (INSN_MIPS32): Delete. (ISA_UNKNOWN): New constant to indicate unknown ISA. (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, ISA_MIPS32): New constants, defined to be the mask of INSN_* constants available at that ISA level. (CPU_UNKNOWN): New constant to indicate unknown CPU. (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, define it with a unique value. (OPCODE_IS_MEMBER): Update for new ISA membership-related constant meanings. * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New definitions. * mips.h (CPU_SB1): New constant.2000-10-20 Jakub Jelinek <jakub@redhat.com> * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. Note that '3' is used for siam operand.2000-09-22 Jim Wilson <wilson@cygnus.com> * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.2000-09-13 Anders Norlander <anorland@acc.umu.se> * mips.h: Use defines instead of hard-coded processor numbers. (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, CPU_4KC, CPU_4KM, CPU_4KP): Define.. (OPCODE_IS_MEMBER): Use new defines. (OP_MASK_SEL, OP_SH_SEL): Define. (OP_MASK_CODE20, OP_SH_CODE20): Define. Add 'P' to used characters. Use 'H' for coprocessor select field. Use 'm' for 20 bit breakpoint code. Document new arg characters and add to used characters. (INSN_MIPS32): New define for MIPS32 extensions. (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.2000-09-05 Alan Modra <alan@linuxcare.com.au> * hppa.h: Mention cz completer.2000-08-16 Jim Wilson <wilson@cygnus.com> * ia64.h (IA64_OPCODE_POSTINC): New.2000-08-15 H.J. Lu <hjl@gnu.org> * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the IgnoreSize change.2000-08-08 Jason Eckhardt <jle@cygnus.com> * i860.h: Small formatting adjustments.2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. Move related opcodes closer to each other. Minor changes in comments, list undefined opcodes.2000-07-26 Dave Brolley <brolley@redhat.com> * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.2000-07-22 Jason Eckhardt <jle@cygnus.com> * i860.h (btne, bte, bla): Changed these opcodes to use sbroff ('r') instead of split16 ('s'). (J, K, L, M): New operand types for 16-bit aligned fields. (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to use I, J, K, L, M instead of just I. (T, U): New operand types for split 16-bit aligned fields. (st.x): Changed these opcodes to use S, T, U instead of just S. (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not exist on the i860. (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. (pfeq.ss, pfeq.dd): New opcodes. (st.s): Fixed incorrect mask bits. (fmlow): Fixed incorrect mask bits. (fzchkl, pfzchkl): Fixed incorrect mask bits. (faddz, pfaddz): Fixed incorrect mask bits. (form, pform): Fixed incorrect mask bits. (pfld.l): Fixed incorrect mask bits. (fst.q): Fixed incorrect mask bits. (all floating point opcodes): Fixed incorrect mask bits for handling of dual bit.2000-07-20 Hans-Peter Nilsson <hp@axis.com> cris.h: New file.2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl>
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