tic30.h

这个是LINUX下的GDB调度工具的源码

/* tic30.h -- Header file for TI TMS320C30 opcode table
   Copyright 1998 Free Software Foundation, Inc.
   Contributed by Steven Haworth ([e-mail])

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
the GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this file; see the file COPYING.  If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA.  */

/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a
   header file.  */

#ifndef _TMS320_H_
#define _TMS320_H_

struct _register
{
  char *name;
  unsigned char opcode;
  unsigned char regtype;
};

typedef struct _register reg;

#define REG_Rn    0x01
#define REG_ARn   0x02
#define REG_DP    0x03
#define REG_OTHER 0x04

static const reg tic30_regtab[] = {
  { "r0", 0x00, REG_Rn },
  { "r1", 0x01, REG_Rn },
  { "r2", 0x02, REG_Rn },
  { "r3", 0x03, REG_Rn },
  { "r4", 0x04, REG_Rn },
  { "r5", 0x05, REG_Rn },
  { "r6", 0x06, REG_Rn },
  { "r7", 0x07, REG_Rn },
  { "ar0",0x08, REG_ARn },
  { "ar1",0x09, REG_ARn },
  { "ar2",0x0A, REG_ARn },
  { "ar3",0x0B, REG_ARn },
  { "ar4",0x0C, REG_ARn },
  { "ar5",0x0D, REG_ARn },
  { "ar6",0x0E, REG_ARn },
  { "ar7",0x0F, REG_ARn },
  { "dp", 0x10, REG_DP },
  { "ir0",0x11, REG_OTHER },
  { "ir1",0x12, REG_OTHER },
  { "bk", 0x13, REG_OTHER },
  { "sp", 0x14, REG_OTHER },
  { "st", 0x15, REG_OTHER },
  { "ie", 0x16, REG_OTHER },
  { "if", 0x17, REG_OTHER },
  { "iof",0x18, REG_OTHER },
  { "rs", 0x19, REG_OTHER },
  { "re", 0x1A, REG_OTHER },
  { "rc", 0x1B, REG_OTHER },
  { "R0", 0x00, REG_Rn },
  { "R1", 0x01, REG_Rn },
  { "R2", 0x02, REG_Rn },
  { "R3", 0x03, REG_Rn },
  { "R4", 0x04, REG_Rn },
  { "R5", 0x05, REG_Rn },
  { "R6", 0x06, REG_Rn },
  { "R7", 0x07, REG_Rn },
  { "AR0",0x08, REG_ARn },
  { "AR1",0x09, REG_ARn },
  { "AR2",0x0A, REG_ARn },
  { "AR3",0x0B, REG_ARn },
  { "AR4",0x0C, REG_ARn },
  { "AR5",0x0D, REG_ARn },
  { "AR6",0x0E, REG_ARn },
  { "AR7",0x0F, REG_ARn },
  { "DP", 0x10, REG_DP },
  { "IR0",0x11, REG_OTHER },
  { "IR1",0x12, REG_OTHER },
  { "BK", 0x13, REG_OTHER },
  { "SP", 0x14, REG_OTHER },
  { "ST", 0x15, REG_OTHER },
  { "IE", 0x16, REG_OTHER },
  { "IF", 0x17, REG_OTHER },
  { "IOF",0x18, REG_OTHER },
  { "RS", 0x19, REG_OTHER },
  { "RE", 0x1A, REG_OTHER },
  { "RC", 0x1B, REG_OTHER },
  { "",   0, 0 }
};

static const reg *const tic30_regtab_end
  = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]);

/* Indirect Addressing Modes Modification Fields */
/* Indirect Addressing with Displacement */
#define PreDisp_Add        0x00
#define PreDisp_Sub        0x01
#define PreDisp_Add_Mod    0x02
#define PreDisp_Sub_Mod    0x03
#define PostDisp_Add_Mod   0x04
#define PostDisp_Sub_Mod   0x05
#define PostDisp_Add_Circ  0x06
#define PostDisp_Sub_Circ  0x07
/* Indirect Addressing with Index Register IR0 */
#define PreIR0_Add         0x08
#define PreIR0_Sub         0x09
#define PreIR0_Add_Mod     0x0A
#define PreIR0_Sub_Mod     0x0B
#define PostIR0_Add_Mod    0x0C
#define PostIR0_Sub_Mod    0x0D
#define PostIR0_Add_Circ   0x0E
#define PostIR0_Sub_Circ   0x0F
/* Indirect Addressing with Index Register IR1 */
#define PreIR1_Add         0x10
#define PreIR1_Sub         0x11
#define PreIR1_Add_Mod     0x12
#define PreIR1_Sub_Mod     0x13
#define PostIR1_Add_Mod    0x14
#define PostIR1_Sub_Mod    0x15
#define PostIR1_Add_Circ   0x16
#define PostIR1_Sub_Circ   0x17
/* Indirect Addressing (Special Cases) */
#define IndirectOnly       0x18
#define PostIR0_Add_BitRev 0x19

typedef struct {
  char *syntax;
  unsigned char modfield;
  unsigned char displacement;
} ind_addr_type;

#define IMPLIED_DISP  0x01
#define DISP_REQUIRED 0x02
#define NO_DISP       0x03

static const ind_addr_type tic30_indaddr_tab[] = {
  { "*+ar",       PreDisp_Add,        IMPLIED_DISP },
  { "*-ar",       PreDisp_Sub,        IMPLIED_DISP },
  { "*++ar",      PreDisp_Add_Mod,    IMPLIED_DISP },
  { "*--ar",      PreDisp_Sub_Mod,    IMPLIED_DISP },
  { "*ar++",      PostDisp_Add_Mod,   IMPLIED_DISP },
  { "*ar--",      PostDisp_Sub_Mod,   IMPLIED_DISP },
  { "*ar++%",     PostDisp_Add_Circ,  IMPLIED_DISP },
  { "*ar--%",     PostDisp_Sub_Circ,  IMPLIED_DISP },
  { "*+ar()",     PreDisp_Add,        DISP_REQUIRED },
  { "*-ar()",     PreDisp_Sub,        DISP_REQUIRED },
  { "*++ar()",    PreDisp_Add_Mod,    DISP_REQUIRED },
  { "*--ar()",    PreDisp_Sub_Mod,    DISP_REQUIRED },
  { "*ar++()",    PostDisp_Add_Mod,   DISP_REQUIRED },
  { "*ar--()",    PostDisp_Sub_Mod,   DISP_REQUIRED },
  { "*ar++()%",   PostDisp_Add_Circ,  DISP_REQUIRED },
  { "*ar--()%",   PostDisp_Sub_Circ,  DISP_REQUIRED },
  { "*+ar(ir0)",  PreIR0_Add,         NO_DISP },
  { "*-ar(ir0)",  PreIR0_Sub,         NO_DISP },
  { "*++ar(ir0)", PreIR0_Add_Mod,     NO_DISP },
  { "*--ar(ir0)", PreIR0_Sub_Mod,     NO_DISP },
  { "*ar++(ir0)", PostIR0_Add_Mod,    NO_DISP },
  { "*ar--(ir0)", PostIR0_Sub_Mod,    NO_DISP },
  { "*ar++(ir0)%",PostIR0_Add_Circ,   NO_DISP },
  { "*ar--(ir0)%",PostIR0_Sub_Circ,   NO_DISP },
  { "*+ar(ir1)",  PreIR1_Add,         NO_DISP },
  { "*-ar(ir1)",  PreIR1_Sub,         NO_DISP },
  { "*++ar(ir1)", PreIR1_Add_Mod,     NO_DISP },
  { "*--ar(ir1)", PreIR1_Sub_Mod,     NO_DISP },
  { "*ar++(ir1)", PostIR1_Add_Mod,    NO_DISP },
  { "*ar--(ir1)", PostIR1_Sub_Mod,    NO_DISP },
  { "*ar++(ir1)%",PostIR1_Add_Circ,   NO_DISP },
  { "*ar--(ir1)%",PostIR1_Sub_Circ,   NO_DISP },
  { "*ar",        IndirectOnly,       NO_DISP },
  { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP },
  { "",           0,0 }
};

static const ind_addr_type *const tic30_indaddrtab_end
  = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]);

/* Possible operand types */
/* Register types */
#define Rn       0x0001
#define ARn      0x0002
#define DPReg    0x0004
#define OtherReg 0x0008
/* Addressing mode types */
#define Direct   0x0010
#define Indirect 0x0020
#define Imm16    0x0040
#define Disp     0x0080
#define Imm24    0x0100
#define Abs24    0x0200
/* 3 operand addressing mode types */
#define op3T1    0x0400
#define op3T2    0x0800
/* Interrupt vector */
#define IVector  0x1000
/* Not required */
#define NotReq   0x2000

#define GAddr1   Rn | Direct | Indirect | Imm16
#define GAddr2   GAddr1 | AllReg
#define TAddr1   op3T1 | Rn | Indirect
#define TAddr2   op3T2 | Rn | Indirect
#define Reg      Rn | ARn
#define AllReg   Reg | DPReg | OtherReg

typedef struct _template
{
  char *name;
  unsigned int operands; /* how many operands */
  unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */
  /* the bits in opcode_modifier are used to generate the final opcode from
     the base_opcode.  These bits also are used to detect alternate forms of
     the same instruction */
  unsigned int opcode_modifier;

  /* opcode_modifier bits: */
#define AddressMode 0x00600000
#define PCRel       0x02000000
#define StackOp     0x001F0000
#define Rotate      StackOp